| Commit message (Expand) | Author | Age |
|---|
| ... | |
| * | Revert commits related to stack warning. | Quentin Colombet | 2013-06-07 |
| * | Explicit triple in warn stack size test cases to not depend on OS. | Quentin Colombet | 2013-06-07 |
| * | Don't cache the instruction and register info from the TargetMachine, because | Bill Wendling | 2013-06-07 |
| * | Don't cache the instruction and register info from the TargetMachine, because | Bill Wendling | 2013-06-07 |
| * | Remove unused c'tor. | Bill Wendling | 2013-06-07 |
| * | R600: Fix calculation of stack offset in AMDGPUFrameLowering | Tom Stellard | 2013-06-07 |
| * | Don't cache the instruction and register info from the TargetMachine, because | Bill Wendling | 2013-06-07 |
| * | R600: Rework subtarget info and remove AMDILDevice classes | Tom Stellard | 2013-06-07 |
| * | Don't cache the instruction and register info from the TargetMachine, because | Bill Wendling | 2013-06-07 |
| * | [docs] Add link to Microsoft PE/COFF Spec. | Rui Ueyama | 2013-06-07 |
| * | Don't cache the instruction and register info from the TargetMachine, because | Bill Wendling | 2013-06-07 |
| * | R600: Fix the fetch limits for R600 generation GPUs | Tom Stellard | 2013-06-07 |
| * | R600: Move Subtarget feature definitions into AMDGPU.td | Tom Stellard | 2013-06-07 |
| * | R600: Remove unnecessary include | Tom Stellard | 2013-06-07 |
| * | Add more explicit link targets to headers in LangRef.rst | Eli Bendersky | 2013-06-07 |
| * | Add a backend option to warn on a given stack size limit. | Quentin Colombet | 2013-06-07 |
| * | ARM FastISel integer sext/zext improvements | JF Bastien | 2013-06-07 |
| * | R600: Don't compare iterators of different maps. | Benjamin Kramer | 2013-06-07 |
| * | Add explicit link targets to some headers in LangRef.rst | Eli Bendersky | 2013-06-07 |
| * | No functionality change. | Manman Ren | 2013-06-07 |
| * | Teach AsmPrinter how to print odd constants. | Quentin Colombet | 2013-06-07 |
| * | DIBuilder: No functionality change. | Manman Ren | 2013-06-07 |
| * | Vincent says the element is at most once in the vector, so we don't need a fu... | Benjamin Kramer | 2013-06-07 |
| * | Use isxdigit. | Rafael Espindola | 2013-06-07 |
| * | Make operator== non-member for greater symmetry. | Rafael Espindola | 2013-06-07 |
| * | Fix a typo in asm string of BP* family of instructions. With this fix | Roman Divacky | 2013-06-07 |
| * | [Object/COFF] BaseOfData field should be absent in PE32+. | Rui Ueyama | 2013-06-07 |
| * | Support OpenBSD's native frame protection conventions. | Rafael Espindola | 2013-06-07 |
| * | R600: Fix a potential iterator invalidation issue. | Benjamin Kramer | 2013-06-07 |
| * | R600: Remove an extra break in R600OptimizeVectorRegisters.cpp | Vincent Lejeune | 2013-06-07 |
| * | [llvm-symbolizer] rewrite r183213 in a more clear way | Alexey Samsonov | 2013-06-07 |
| * | BitVector: Do the right thing in all() when Size is a multiple of BITWORD_SIZE. | Benjamin Kramer | 2013-06-07 |
| * | Optimize BitVector::all(). | Benjamin Kramer | 2013-06-07 |
| * | Fold variable that's only used in assert into the assert. | Benjamin Kramer | 2013-06-07 |
| * | Add a script to help us create source tar balls for the release. | Bill Wendling | 2013-06-07 |
| * | Use proper exit code. | Bill Wendling | 2013-06-07 |
| * | Correct wrong register in this example, pointed out by Baoshan Pang. | Duncan Sands | 2013-06-07 |
| * | Don't cache the instruction and register info from the TargetMachine, because | Bill Wendling | 2013-06-07 |
| * | Don't cache the instruction and register info from the TargetMachine, because | Bill Wendling | 2013-06-07 |
| * | Don't cache the instruction and register info from the TargetMachine, because | Bill Wendling | 2013-06-07 |
| * | Don't cache the instruction and register info from the TargetMachine, because | Bill Wendling | 2013-06-07 |
| * | Don't cache the instruction and register info from the TargetMachine, because | Bill Wendling | 2013-06-07 |
| * | [objc-arc] Ensure that the cfg path count does not overflow when we multiply ... | Michael Gottesman | 2013-06-07 |
| * | Don't cache the instruction and register info from the TargetMachine, because | Bill Wendling | 2013-06-07 |
| * | Don't cache the instruction info and register info objects. | Bill Wendling | 2013-06-07 |
| * | DIBuilder: No functionality change. | Manman Ren | 2013-06-07 |
| * | ARM sched model: Use the right resources for DIV | Arnold Schwaighofer | 2013-06-07 |
| * | ARM sched model: Add VFP div instruction on Swift | Arnold Schwaighofer | 2013-06-07 |
| * | CodeGenSchedule: Use resize instead of copying a vector | Arnold Schwaighofer | 2013-06-07 |
| * | ARM sched model: Add SIMD/VFP load/store instructions on Swift | Arnold Schwaighofer | 2013-06-07 |
