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path: root/include/llvm/CodeGen/MachineOperand.h
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* MachineOperand::setIsDebug should ensure the register is /not/ a definitionDavid Blaikie2013-06-16
| | | | | | | | | | This currently unused function appeared to be asserting in the wrong direction - DebugValues are never definitions of registers, only uses. Curiously we don't perform any of these checks for the more common (& actually used) case of MachineOperand::CreateReg (or other Create functions). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184065 91177308-0d34-0410-b5e6-96231b3b80d8
* Pack MachineOperand bitfields better.Jakob Stoklund Olesen2013-01-07
| | | | | | Previously, 4 bits were unused. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171814 91177308-0d34-0410-b5e6-96231b3b80d8
* Use ArrayRecycler for MachineInstr operand lists.Jakob Stoklund Olesen2013-01-05
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Instead of an std::vector<MachineOperand>, use MachineOperand arrays from an ArrayRecycler living in MachineFunction. This has several advantages: - MachineInstr now has a trivial destructor, making it possible to delete them in batches when destroying MachineFunction. This will be enabled in a later patch. - Bypassing malloc() and free() can be faster, depending on the system library. - MachineInstr objects and their operands are allocated from the same BumpPtrAllocator, so they will usually be next to each other in memory, providing better locality of reference. - Reduce MachineInstr footprint. A std::vector is 24 bytes, the new operand array representation only uses 8+4+1 bytes in MachineInstr. - Better control over operand array reallocations. In the old representation, the use-def chains would be reordered whenever a std::vector reached its capacity. The new implementation never changes the use-def chain order. Note that some decisions in the code generator depend on the use-def chain orders, so this patch may cause different assembly to be produced in a few cases. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171598 91177308-0d34-0410-b5e6-96231b3b80d8
* Add extra declarations of hash_value needed to build llvm with xlc 12.1.Rafael Espindola2012-10-31
| | | | | | Patch by Kai! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167085 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix PR11985Michael Liao2012-09-12
| | | | | | | | | | | | | - BlockAddress has no support of BA + offset form and there is no way to propagate that offset into machine operand; - Add BA + offset support and a new interface 'getTargetBlockAddress' to simplify target block address forming; - All targets are modified to use new interface and X86 backend is enhanced to support BA + offset addressing. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163743 91177308-0d34-0410-b5e6-96231b3b80d8
* Clean up includes.Benjamin Kramer2012-09-05
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163229 91177308-0d34-0410-b5e6-96231b3b80d8
* Allow tied uses and defs in different orders.Jakob Stoklund Olesen2012-09-04
| | | | | | | | | | | | | | | | After much agonizing, use a full 4 bits of precious MachineOperand space to encode this. This uses existing padding, and doesn't grow MachineOperand beyond its current 32 bytes. This allows tied defs among the first 15 operands on a normal instruction, just like the current MCInstrDesc constraint encoding. Inline assembly needs to be able to tie more than the first 15 operands, and gets special treatment. Tied uses can appear beyond 15 operands, as long as they are tied to a def that's in range. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163151 91177308-0d34-0410-b5e6-96231b3b80d8
* Add MachineInstr::tieOperands, remove setIsTied().Jakob Stoklund Olesen2012-08-31
| | | | | | | | | | | Manage tied operands entirely internally to MachineInstr. This makes it possible to change the representation of tied operands, as I will do shortly. The constraint that tied uses and defs must be in the same order was too restrictive. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163021 91177308-0d34-0410-b5e6-96231b3b80d8
* Add a MachineOperand::isTied() flag.Jakob Stoklund Olesen2012-08-28
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | While in SSA form, a MachineInstr can have pairs of tied defs and uses. The tied operands are used to represent read-modify-write operands that must be assigned the same physical register. Previously, tied operand pairs were computed from fixed MCInstrDesc fields, or by using black magic on inline assembly instructions. The isTied flag makes it possible to add tied operands to any instruction while getting rid of (some of) the inlineasm magic. Tied operands on normal instructions are needed to represent predicated individual instructions in SSA form. An extra <tied,imp-use> operand is required to represent the output value when the instruction predicate is false. Adding a predicate to: %vreg0<def> = ADD %vreg1, %vreg2 Will look like: %vreg0<tied,def> = ADD %vreg1, %vreg2, pred:3, %vreg7<tied,imp-use> The virtual register %vreg7 is the value given to %vreg0 when the predicate is false. It will be assigned the same physreg as %vreg0. This commit adds the isTied flag and sets it based on MCInstrDesc when building an instruction. The flag is not used for anything yet. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162774 91177308-0d34-0410-b5e6-96231b3b80d8
* Don't allow TargetFlags on MO_Register MachineOperands.Jakob Stoklund Olesen2012-08-28
| | | | | | | | | | | | Register operands are manipulated by a lot of target-independent code, and it is not always possible to preserve target flags. That means it is not safe to use target flags on register operands. None of the targets in the tree are using register operand target flags. External targets should be using immediate operands to annotate instructions with operand modifiers. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162770 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix integer undefined behavior due to signed left shift overflow in LLVM.Richard Smith2012-08-24
| | | | | | | Reviewed offline by chandlerc. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162623 91177308-0d34-0410-b5e6-96231b3b80d8
* Reapply r161633-161634 "Partition use lists so defs always come before uses.""Jakob Stoklund Olesen2012-08-10
| | | | | | | No changes to these patches, MRI needed to be notified when changing uses into defs and vice versa. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161644 91177308-0d34-0410-b5e6-96231b3b80d8
* Also update MRI use lists when changing a use to a def and vice versa.Jakob Stoklund Olesen2012-08-10
| | | | | | This was the cause of the buildbot failures. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161643 91177308-0d34-0410-b5e6-96231b3b80d8
* Revert r161633-161634 "Partition use lists so defs always come before uses."Jakob Stoklund Olesen2012-08-09
| | | | | | These commits broke a number of buildbots. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161640 91177308-0d34-0410-b5e6-96231b3b80d8
* Don't use pointer-pointers for the register use lists.Jakob Stoklund Olesen2012-08-09
| | | | | | | | | | | Use a more conventional doubly linked list where the Prev pointers form a cycle. This means it is no longer necessary to adjust the Prev pointers when reallocating the VRegInfo array. The test changes are required because the register allocation hint is using the use-list order to break ties. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161633 91177308-0d34-0410-b5e6-96231b3b80d8
* Move use list management into MachineRegisterInfo.Jakob Stoklund Olesen2012-08-09
| | | | | | | | | | | | | | Register MachineOperands are kept in linked lists accessible via MRI's reg_iterator interfaces. The linked list management was handled partly by MachineOperand methods, partly by MRI methods. Move all of the list management into MRI, delete MO::AddRegOperandToRegInfo() and MO::RemoveRegOperandFromRegInfo(). Be more explicit about handling the cases where an MRI pointer isn't available. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161632 91177308-0d34-0410-b5e6-96231b3b80d8
* MachineRegisterInfo was already a friend of MachineOperand, and GCC complainsMatt Beaumont-Gay2012-08-09
| | | | | | about repeated friending. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161553 91177308-0d34-0410-b5e6-96231b3b80d8
* Move getNextOperandForReg() into MachineRegisterInfo.Jakob Stoklund Olesen2012-08-08
| | | | | | | MRI provides iterators for traversing the use-def chains. They should not be accessible from anywhere else. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161543 91177308-0d34-0410-b5e6-96231b3b80d8
* Add a new kind of MachineOperand: MO_TargetIndex.Jakob Stoklund Olesen2012-08-07
| | | | | | | | | | | | A target index operand looks a lot like a constant pool reference, but it is completely target-defined. It contains the 8-bit TargetFlags, a 32-bit index, and a 64-bit offset. It is preserved by all code generator passes. TargetIndex operands can be used to carry target-specific information in cases where immediate operands won't suffice. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161441 91177308-0d34-0410-b5e6-96231b3b80d8
* Put up warning signs around MO::getNextOperandForReg().Jakob Stoklund Olesen2012-08-06
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161329 91177308-0d34-0410-b5e6-96231b3b80d8
* Finish fixing the MachineOperand hashing, providing a nice modernChandler Carruth2012-07-05
| | | | | | | | | | | | | | | | | | | | | | | | | | | | hash_value overload for MachineOperands. This addresses a FIXME sufficient for me to remove it, and cleans up the code nicely too. The important changes to the hashing logic: - TargetFlags are now included in all of the hashes. These were complete missed. - Register operands have their subregisters and whether they are a def included in the hash. - We now actually hash all of the operand types. Previously, many operand types were simply *dropped on the floor*. For example: - Floating point immediates - Large integer immediates (>64-bit) - External globals! - Register masks - Metadata operands - It removes the offset from the block-address hash; I'm a bit suspicious of this, but isIdenticalTo doesn't consider the offset for black addresses. Any patterns involving these entities could have triggered extreme slowdowns in MachineCSE or PHIElimination. Let me know if there are PRs you think might be closed now... I'm looking myself, but I may miss them. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159743 91177308-0d34-0410-b5e6-96231b3b80d8
* Add internal read flags to MachineInstrBuilder and hook them into the ↵Pete Cooper2012-06-07
| | | | | | MachineOperand flag of the same name git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158137 91177308-0d34-0410-b5e6-96231b3b80d8
* Clean up comment.Jakob Stoklund Olesen2012-02-10
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150262 91177308-0d34-0410-b5e6-96231b3b80d8
* Add a static MachineOperand::clobbersPhysReg().Jakob Stoklund Olesen2012-02-10
| | | | | | | | It can be necessary to detach a register mask pointer from its MachineOperand. This method is convenient for checking clobbered physregs on a detached bitmask pointer. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150261 91177308-0d34-0410-b5e6-96231b3b80d8
* Require non-NULL register masks.Jakob Stoklund Olesen2012-02-02
| | | | | | | It doesn't seem worthwhile to give meaning to a NULL register mask pointer. It complicates all the code using register mask operands. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149646 91177308-0d34-0410-b5e6-96231b3b80d8
* Add a new kind of MachineOperand: MO_RegisterMask.Jakob Stoklund Olesen2012-01-16
| | | | | | | | | | | | | | | | | | | | | Register masks will be used as a compact representation of large clobber lists. Currently, an x86 call instruction has some 40 operands representing call-clobbered registers. That's more than 1kB of useless operands per call site. A register mask operand references a bit mask of call-preserved registers, everything else is clobbered. The bit mask will typically come from TargetRegisterInfo::getCallPreservedMask(). By abandoning ImplicitDefs for call-clobbered registers, it also becomes possible to share call instruction descriptions between calling conventions, and we can get rid of the WINCALL* instructions. This patch introduces the new operand kind. Future patches will add RegMask support to target-independent passes before finally the fixed clobber lists can be removed from call instruction descriptions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148250 91177308-0d34-0410-b5e6-96231b3b80d8
* Add MachineOperand IsInternalRead flag.Jakob Stoklund Olesen2011-12-07
| | | | | | | This flag is used when bundling machine instructions. It indicates whether the operand reads a value defined inside or outside its bundle. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145997 91177308-0d34-0410-b5e6-96231b3b80d8
* Allow <undef> flags on def operands as well as uses.Jakob Stoklund Olesen2011-10-04
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The <undef> flag says that a MachineOperand doesn't read its register, or doesn't depend on the previous value of its register. A full register def never depends on the previous register value. A partial register def may depend on the previous value if it is intended to update part of a register. For example: %vreg10:dsub_0<def,undef> = COPY %vreg1 %vreg10:dsub_1<def> = COPY %vreg2 The first copy instruction defines the full %vreg10 register with the bits not covered by dsub_0 defined as <undef>. It is not considered a read of %vreg10. The second copy modifies part of %vreg10 while preserving the rest. It has an implicit read of %vreg10. This patch adds a MachineOperand::readsReg() method to determine if an operand reads its register. Previously, this was modelled by adding a full-register <imp-def> operand to the instruction. This approach makes it possible to determine directly from a MachineOperand if it reads its register. No scanning of MI operands is required. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141124 91177308-0d34-0410-b5e6-96231b3b80d8
* Handle debug info for i128 constants.Devang Patel2011-06-24
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133821 91177308-0d34-0410-b5e6-96231b3b80d8
* Comment cleanup.Eric Christopher2011-05-26
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132162 91177308-0d34-0410-b5e6-96231b3b80d8
* Frame indices are signed. Update MachineOperand methods accordingly.Jim Grosbach2011-05-17
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131475 91177308-0d34-0410-b5e6-96231b3b80d8
* Simplify LiveDebugVariables by storing MachineOperand copies locations insteadJakob Stoklund Olesen2011-01-09
| | | | | | | | | | | | | | of using a Location class with the same information. When making a copy of a MachineOperand that was already stored in a MachineInstr, it is necessary to clear the parent pointer on the copy. Otherwise the register use-def lists become inconsistent. Add MachineOperand::clearParent() to do that. An alternative would be a custom MachineOperand copy constructor that cleared ParentMI. I didn't want to do that because of the performance impact. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123109 91177308-0d34-0410-b5e6-96231b3b80d8
* Merge System into Support.Michael J. Spencer2010-11-29
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120298 91177308-0d34-0410-b5e6-96231b3b80d8
* Shrink MachineOperand from 40 to 32 bytes on 64-bit hosts.Jakob Stoklund Olesen2010-10-19
| | | | | | | | | | | | | Pull an unsigned out of the Contents union such that it has the same size as two pointers and no padding. Arrange members such that the Contents union and all pointers can be 8-byte aligned without padding. This speeds up code generation by 0.8% on a 64-bit host. 32-bit hosts should be unaffected. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116857 91177308-0d34-0410-b5e6-96231b3b80d8
* trailing whitespaceJim Grosbach2010-09-15
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113975 91177308-0d34-0410-b5e6-96231b3b80d8
* Add a TargetRegisterInfo::composeSubRegIndices hook with a defaultJakob Stoklund Olesen2010-05-28
| | | | | | | | | | implementation that is correct for most targets. Tablegen will override where needed. Add MachineOperand::subst{Virt,Phys}Reg methods that correctly handle existing subreg indices when sustituting registers. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104985 91177308-0d34-0410-b5e6-96231b3b80d8
* Add const qualifiers to CodeGen's use of LLVM IR constructs.Dan Gohman2010-04-15
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101334 91177308-0d34-0410-b5e6-96231b3b80d8
* Change how dbg_value sdnodes are converted into machine instructions. Their ↵Evan Cheng2010-03-25
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | placement should be determined by the relative order of incoming llvm instructions. The scheduler will now use the SDNode ordering information to determine where to insert them. A dbg_value instruction is inserted after the instruction with the last highest source order and before the instruction with the next highest source order. It will optimize the placement by inserting right after the instruction that produces the value if they have consecutive order numbers. Here is a theoretical example that illustrates why the placement is important. tmp1 = store tmp1 -> x ... tmp2 = add ... ... call ... store tmp2 -> x Now mem2reg comes along: tmp1 = dbg_value (tmp1 -> x) ... tmp2 = add ... ... call ... dbg_value (tmp2 -> x) When the debugger examine the value of x after the add instruction but before the call, it should have the value of tmp1. Furthermore, for dbg_value's that reference constants, they should not be emitted at the beginning of the block (since they do not have "producers"). This patch also cleans up how SDISel manages DbgValue nodes. It allow a SDNode to be referenced by multiple SDDbgValue nodes. When a SDNode is deleted, it uses the information to find the SDDbgValues and invalidate them. They are not deleted until the corresponding SelectionDAG is destroyed. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99469 91177308-0d34-0410-b5e6-96231b3b80d8
* add support for MCSymbols as operands to MachineInstrs.Chris Lattner2010-03-13
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98433 91177308-0d34-0410-b5e6-96231b3b80d8
* Ordering forward declarations.Evan Cheng2010-03-03
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97626 91177308-0d34-0410-b5e6-96231b3b80d8
* Further constify MDNode* references.Dale Johannesen2010-02-26
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97252 91177308-0d34-0410-b5e6-96231b3b80d8
* Allow isDebug inquiry on any MO.Dale Johannesen2010-02-10
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@95818 91177308-0d34-0410-b5e6-96231b3b80d8
* Add isDebug argument to ChangeToRegister; this preventsDale Johannesen2010-02-10
| | | | | | | | the field from being used uninitialized later in some cases. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@95735 91177308-0d34-0410-b5e6-96231b3b80d8
* Debug operands should not be def or kill.Dale Johannesen2010-02-09
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@95632 91177308-0d34-0410-b5e6-96231b3b80d8
* Add a Debug bit to MachineOperand, for uses thatDale Johannesen2010-02-06
| | | | | | | | | | are from debug info. Add an iterator to MachineRegisterInfo to skip Debug operands when walking the use list. No functional change yet. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@95473 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove unneeded argument per review.Dale Johannesen2010-01-15
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@93579 91177308-0d34-0410-b5e6-96231b3b80d8
* Further progration of metadata operands. TheDale Johannesen2010-01-13
| | | | | | | | | dumper doesn't really do what I want yet, but at least it doesn't crash now. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@93272 91177308-0d34-0410-b5e6-96231b3b80d8
* Add MO_Metadata as an operand kind. Not used yet.Dale Johannesen2010-01-12
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@93220 91177308-0d34-0410-b5e6-96231b3b80d8
* Target-independent support for TargetFlags on BlockAddress operands,Dan Gohman2009-11-20
| | | | | | | and support for blockaddresses in x86-32 PIC mode. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@89506 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove dead code.Devang Patel2009-10-30
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85551 91177308-0d34-0410-b5e6-96231b3b80d8
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