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path: root/include/llvm/CodeGen/ScheduleDAG.h
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* Sort the #include lines for the include/... tree with the script.Chandler Carruth2012-12-03
* misched: Don't consider artificial edges weak edges.Andrew Trick2012-11-13
* misched: Infrastructure for weak DAG edges.Andrew Trick2012-11-12
* misched: TargetSchedule interface for machine resources.Andrew Trick2012-11-06
* ScheduleDAG interface. Added OrderKind to distinguish nonregister dependencies.Andrew Trick2012-11-06
* misched: Use the TargetSchedModel interface wherever possible.Andrew Trick2012-10-10
* misched: remove forceUnitLatencies. Defaults are handled by the default Sched...Andrew Trick2012-10-08
* Simplify the computeOperandLatency API.Andrew Trick2012-08-23
* sched: Avoid trivially redundant DAG edges. Take the one with higher latency.Andrew Trick2012-06-13
* misched: API for minimum vs. expected latency.Andrew Trick2012-06-05
* misched: implemented a framework for top-down or bottom-up scheduling.Andrew Trick2012-03-14
* misched preparation: rename core scheduler methods for consistency.Andrew Trick2012-03-07
* misched preparation: clarify ScheduleDAG and ScheduleDAGInstrs roles.Andrew Trick2012-03-07
* misched preparation: modularize schedule emission.Andrew Trick2012-03-07
* misched preparation: modularize schedule printing.Andrew Trick2012-03-07
* misched preparation: modularize schedule verification.Andrew Trick2012-03-07
* Cleanup in preparation for misched: Move DAG visualization logic.Andrew Trick2012-03-07
* Cleanup: DAG building is specific to either SD or MI scheduling. Not part of ...Andrew Trick2012-03-07
* misched commentsAndrew Trick2012-03-07
* Initialize SUnits before DAG building.Andrew Trick2012-02-22
* Move some llvm_unreachable's from r149849 out of switch statements to satisfy...Craig Topper2012-02-06
* Convert assert(0) to llvm_unreachableCraig Topper2012-02-05
* Move Sched::Preference out of TargetMachine.h where it is not referenced.Evan Cheng2012-01-12
* Unweaken vtables as per http://llvm.org/docs/CodingStandards.html#ll_virtual_...David Blaikie2011-12-20
* - Rename TargetInstrDesc, TargetOperandInfo to MCInstrDesc and MCOperandInfo andEvan Cheng2011-06-28
* Added -stress-sched flag in the Asserts build.Andrew Trick2011-06-15
* Remove dead code.Devang Patel2011-06-02
* Be careful about scheduling nodes above previous calls. It increase usages ofEvan Cheng2011-04-26
* Fix a ton of comment typos found by codespell. Patch byChris Lattner2011-04-15
* In the pre-RA scheduler, maintain cmp+br proximity.Andrew Trick2011-04-14
* Added a check in the preRA scheduler for potential interference on aAndrew Trick2011-04-07
* Typos.Eric Christopher2011-03-07
* Introducing a new method of tracking register pressure. We can'tAndrew Trick2011-02-04
* Header warning patrol.Eric Christopher2010-12-25
* Minor cleanup related to my latest scheduler changes.Andrew Trick2010-12-24
* Various bits of framework needed for precise machine-level selectionAndrew Trick2010-12-24
* whitespaceAndrew Trick2010-12-24
* update comment.Chris Lattner2010-12-20
* SDep is POD-like. Shave off a few bytes from SUnit by moving a member around.Benjamin Kramer2010-11-25
* Two sets of changes. Sorry they are intermingled.Evan Cheng2010-11-03
* Change push_all to a non-virtual function and implement it in theDan Gohman2010-05-26
* Delete an unused function.Dan Gohman2010-05-26
* Allow targets more controls on what nodes are scheduled by reg pressure, what...Evan Cheng2010-05-20
* Add a hybrid bottom up scheduler that reduce register usage while avoidingEvan Cheng2010-05-20
* Fix the post-RA instruction scheduler to handle instructions referenced byJim Grosbach2010-05-19
* Remove unused member variable.Zhongxing Xu2010-05-17
* Get rid of the EdgeMapping map. Instead, just check for BasicBlockDan Gohman2010-05-01
* Delete an unused member variable.Dan Gohman2010-04-13
* trim some prototypes.Chris Lattner2010-04-05
* Progress towards shepherding debug info through SelectionDAG.Dale Johannesen2010-03-10