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path: root/include/llvm/CodeGen/ScheduleDAGInstrs.h
Commit message (Expand)AuthorAge
* Re-sort all of the includes with ./utils/sort_includes.py so thatChandler Carruth2014-01-07
* Move the PostRA scheduler's fixupKills function for reuse.Andrew Trick2013-12-28
* Correct word hyphenationsAlp Toker2013-12-05
* Even more spelling fixes for "instruction".Robert Wilhelm2013-09-28
* mi-sched: Precompute a PressureDiff for each instruction, adjust for liveness...Andrew Trick2013-08-30
* Comment and revise the cyclic critical path code.Andrew Trick2013-08-29
* Adds cyclic critical path computation and heuristics, temporarily disabled.Andrew Trick2013-08-23
* MI Sched: record local vreg uses.Andrew Trick2013-08-23
* Remove unused field.Andrew Trick2013-08-23
* mi-sched: Don't call MBB.size() in initSUnits. The driver already has instr c...Andrew Trick2013-08-23
* Machine Model: Add MicroOpBufferSize and resource BufferSize.Andrew Trick2013-06-15
* MI Sched: eliminate local vreg copies.Andrew Trick2013-04-24
* Comment a strange field in ScheduleDAG.Andrew Trick2013-04-23
* Cleanup #includes.Jakub Staszak2013-03-10
* Introduce a new data structure, the SparseMultiSet, and changes to the MI sch...Michael Ilseman2013-01-21
* Fix include guards so they exactly match file names.Jakub Staszak2013-01-10
* Sort the #include lines for the include/... tree with the script.Chandler Carruth2012-12-03
* misched: TargetSchedule interface for machine resources.Andrew Trick2012-11-06
* misched: Use the TargetSchedModel interface wherever possible.Andrew Trick2012-10-10
* misched: Remove LoopDependencies heuristic.Andrew Trick2012-10-09
* TargetSchedModel API. Implement latency lookup, disabled.Andrew Trick2012-09-18
* Revert r164061-r164067. Most of the new subtarget emitter.Andrew Trick2012-09-17
* TargetSchedModel API. Implement latency lookup, disabled.Andrew Trick2012-09-17
* Simplify the computeOperandLatency API.Andrew Trick2012-08-23
* Remove unused private fields found by clang's new -Wunused-private-field.Benjamin Kramer2012-06-06
* misched: API for minimum vs. expected latency.Andrew Trick2012-06-05
* Fix typos found by http://github.com/lyda/misspell-checkBenjamin Kramer2012-06-02
* misched: DAG builder support for tracking register pressure within the curren...Andrew Trick2012-04-24
* SparseSet: Add support for key-derived indexes and arbitrary key types.Andrew Trick2012-04-20
* misched: Added CanHandleTerminators.Andrew Trick2012-04-13
* misched: Add finalizeScheduler to complete the target interface.Andrew Trick2012-04-01
* misched interface: rename Begin/End to RegionBegin/RegionEnd since they are n...Andrew Trick2012-03-09
* Cleanup VLIWPacketizer to use the updated ScheduleDAGInstrs interface.Andrew Trick2012-03-07
* misched prep: Expose the ScheduleDAGInstrs interface so targets mayAndrew Trick2012-03-07
* Move ScheduleDAGInstrs.h to be a private header. Front-endsDan Gohman2009-02-06
* If a vector is empty, you're not allowed to access anyDuncan Sands2009-01-20
* Move a few containers out of ScheduleDAGInstrs::BuildSchedGraphDan Gohman2009-01-15
* Rename BuildSchedUnits to BuildSchedGraph, and refactor theDan Gohman2008-12-23
* Add an assertion to the ScheduleDAGInstrs class to catch SUnitsDan Gohman2008-12-22
* Fix some register-alias-related bugs in the post-RA scheduler livenessDan Gohman2008-12-16
* Rewrite the SDep class, and simplify some of the related code.Dan Gohman2008-12-09
* Implement ComputeLatency for MachineInstr ScheduleDAGs. FactorDan Gohman2008-11-21
* Experimental post-pass scheduling support. Post-pass schedulingDan Gohman2008-11-19