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path: root/include/llvm/CodeGen
Commit message (Expand)AuthorAge
* CodeGen: Emit a libcall if the target doesn't support 16-byte wide atomicsDavid Majnemer2013-10-18
* Add support for metadata representing .ident directives.Rafael Espindola2013-10-16
* Simplify formatting and sort these. No functionality changed.Chandler Carruth2013-10-15
* LiveRegUnits: Use *MBB for consistency and convenience.Andrew Trick2013-10-14
* Use a SparseSet in LiveRegUnits.Andrew Trick2013-10-14
* Move LiveRegUnits implementation into .cpp. Comment and format.Andrew Trick2013-10-14
* Remove extra indentation in LiveRegUnits.Andrew Trick2013-10-14
* Convert LiveRegUnits methods to the current convention (it's new code).Andrew Trick2013-10-14
* Remove the now unused strong phi elimination pass.Rafael Espindola2013-10-14
* Introduce ad hoc liveness tracking utility: LiveRegUnitsMatthias Braun2013-10-11
* Make AsmPrinter::emitImplicitDef a virtual method so targets can emit custom ...Justin Holewinski2013-10-11
* Print register in LiveInterval::print()Matthias Braun2013-10-10
* Represent RegUnit liveness with LiveRange instanceMatthias Braun2013-10-10
* Work on LiveRange instead of LiveInterval where possibleMatthias Braun2013-10-10
* Pass LiveQueryResult by valueMatthias Braun2013-10-10
* Refactor LiveInterval: introduce new LiveRange classMatthias Braun2013-10-10
* Rename LiveRange to LiveInterval::SegmentMatthias Braun2013-10-10
* Rename parameter: defined regs are not incoming.Matthias Braun2013-10-10
* Implement AArch64 vector load/store multiple N-element structure class SIMD(l...Hao Liu2013-10-10
* Revert "Implement AArch64 vector load/store multiple N-element structure clas...Rafael Espindola2013-10-10
* Implement AArch64 vector load/store multiple N-element structure class SIMD(l...Hao Liu2013-10-10
* Explicitly request unsigned enum types when desiredReid Kleckner2013-10-08
* Implement aarch64 neon instruction set AdvSIMD (Across).Jiangning Liu2013-10-05
* Add OPC_CheckChildSame0-3 to the DAG isel matcher. This replaces sequences of...Craig Topper2013-10-05
* Revert r191940 to see if it fixes the build bots.Craig Topper2013-10-04
* Add OPC_CheckChildSame0-3 to the DAG isel matcher. This replaces sequences of...Craig Topper2013-10-04
* Add v4f16 to supported value types.Pete Cooper2013-10-03
* IfConverter: Use TargetSchedule for instruction latenciesArnold Schwaighofer2013-09-30
* Remove an old workaround for a compiler that EOL'd years ago.Benjamin Kramer2013-09-29
* Allocate AtomicSDNode operands in SelectionDAG's allocator to stop leakage.Benjamin Kramer2013-09-29
* Even more spelling fixes for "instruction".Robert Wilhelm2013-09-28
* [stackprotector] Refactor the StackProtector pass from a single .cpp file int...Josh Magee2013-09-27
* [ARM] Use the load-acquire/store-release instructions optimally in AArch32.Amara Emerson2013-09-26
* Initial support for Neon scalar instructions.Jiangning Liu2013-09-24
* Allow subtarget selection of the default MachineScheduler and document the in...Andrew Trick2013-09-20
* simplify expressionAdrian Prantl2013-09-17
* Debug info: Fix PR16736 and rdar://problem/14990587.Adrian Prantl2013-09-16
* Add an instruction deprecation feature to TableGen.Joey Gouly2013-09-12
* white spaces and long linesJack Carter2013-09-09
* mi-sched: cleanup register pressure update, remove a FIXME.Andrew Trick2013-09-06
* Added MachineSchedPolicy.Andrew Trick2013-09-06
* avoid unnecessary direct access to LiveInterval::rangesMatthias Braun2013-09-06
* remove unused argument from LiveRanges::join()Matthias Braun2013-09-06
* fix typo in commentMatthias Braun2013-09-06
* mi-sched: Suppress register pressure tracking when the scheduling window is t...Andrew Trick2013-09-04
* mi-sched: bypass heuristic checks when regpressure tracking is disabled.Andrew Trick2013-09-04
* Added -misched-regpressure option.Andrew Trick2013-09-04
* Fix grammarMatt Arsenault2013-09-03
* Free PressureDiffs instead of leaking.Benjamin Kramer2013-08-31
* Use LiveRangeQuery for instruction-level liveness queries.Andrew Trick2013-08-30