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	Commit message (Expand)	Author	Age
*	Added instregex support to TableGen subtarget emitter.	Andrew Trick	2012-10-03
*	Machine Model (-schedmodel only). Added SchedAliases.	Andrew Trick	2012-09-22
*	misched: Generic tablegen classes for the new machine model.	Andrew Trick	2012-09-14
*	comment	Andrew Trick	2012-09-14
*	Added MispredictPenalty to SchedMachineModel.	Andrew Trick	2012-08-08
*	I'm introducing a new machine model to simultaneously allow simple	Andrew Trick	2012-07-07
*	Reapply "Make NumMicroOps a variable in the subtarget's instruction itinerary."	Andrew Trick	2012-07-02
*	Revert "Make NumMicroOps a variable in the subtarget's instruction itinerary."	Andrew Trick	2012-06-29
*	Make NumMicroOps a variable in the subtarget's instruction itinerary.	Andrew Trick	2012-06-29
*	Use "NoItineraries" for processors with no itineraries.	Andrew Trick	2012-06-22
*	misched: Added MultiIssueItineraries.	Andrew Trick	2012-06-05
*	whitespace	Andrew Trick	2012-06-05
*	Comments about operand cycles and pipeline forwarding pathes.	Evan Cheng	2010-09-30
*	Add support to model pipeline bypass / forwarding.	Evan Cheng	2010-09-28
*	For each instruction itinerary class, specify the number of micro-ops each	Evan Cheng	2010-09-09
*	Make processor FUs unique for given itinerary. This extends the limit of 32	Anton Korobeynikov	2010-04-18
*	Since tblgen bug was fixed (thanks Jakob!) we don't need InstrStage2 hack any...	Anton Korobeynikov	2010-04-07
*	Make use of new reserved/required scheduling stuff: introduce VFP and NEON lo...	Anton Korobeynikov	2010-04-07
*	Initial support for different kinds of FU reservation.	Anton Korobeynikov	2010-04-07
*	Fix apostrophos.	Dan Gohman	2009-09-15
*	Extend the instruction itinerary model to include the ability to indicate the...	David Goodwin	2009-08-17
*	Enhance the InstrStage object to enable the specification of an Itinerary wit...	David Goodwin	2009-08-12
*	Move target independent td files from lib/Target/ to include/llvm/Target so t...	Evan Cheng	2008-11-24