summaryrefslogtreecommitdiff
path: root/lib/CodeGen/RegisterScavenging.cpp
Commit message (Collapse)AuthorAge
* RegScavenger should not exclude undef usesHal Finkel2013-07-11
| | | | | | | | | | | | | | When computing currently-live registers, the register scavenger excludes undef uses. As a result, undef uses are ignored when computing the restore points of registers spilled into the emergency slots. While the register scavenger normally excludes from consideration, when scavenging, registers used by the current instruction, we need to not exclude undef uses. Otherwise, we might end up requiring more emergency spill slots than we have (in the case where the undef use *is* the currently-spilled register). Another bug found by llvm-stress. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186067 91177308-0d34-0410-b5e6-96231b3b80d8
* Use SmallVectorImpl instead of SmallVector for iterators and references to ↵Craig Topper2013-07-03
| | | | | | avoid specifying the vector size unnecessarily. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185512 91177308-0d34-0410-b5e6-96231b3b80d8
* Simplify logic now that r182490 is in place. No functional change intended.Chad Rosier2013-05-22
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182531 91177308-0d34-0410-b5e6-96231b3b80d8
* Reapply r178845 with fix - Fix bug in PEI's virtual-register scavengingHal Finkel2013-04-05
| | | | | | | | | | | | | | | | | | | | | | | | | | | | This fixes PEI as previously described, but correctly handles the case where the instruction defining the virtual register to be scavenged is the first in the block. Arnold provided me with a bugpoint-reduced test case, but even that seems too large to use as a regression test. If I'm successful in cleaning it up then I'll commit that as well. Original commit message: This change fixes a bug that I introduced in r178058. After a register is scavenged using one of the available spills slots the instruction defining the virtual register needs to be moved to after the spill code. The scavenger has already processed the defining instruction so that registers killed by that instruction are available for definition in that same instruction. Unfortunately, after this, the scavenger needs to iterate through the spill code and then visit, again, the instruction that defines the now-scavenged register. In order to avoid confusion, the register scavenger needs the ability to 'back up' through the spill code so that it can again process the instructions in the appropriate order. Prior to this fix, once the scavenger reached the just-moved instruction, it would assert if it killed any registers because, having already processed the instruction, it believed they were undefined. Unfortunately, I don't yet have a small test case. Thanks to Pranav Bhandarkar for diagnosing the problem and testing this fix. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178919 91177308-0d34-0410-b5e6-96231b3b80d8
* Revert r178845 - Fix bug in PEI's virtual-register scavengingHal Finkel2013-04-05
| | | | | | | | | | | | | | | | | | | | | | Reverting because this breaks one of the LTO builders. Original commit message: This change fixes a bug that I introduced in r178058. After a register is scavenged using one of the available spills slots the instruction defining the virtual register needs to be moved to after the spill code. The scavenger has already processed the defining instruction so that registers killed by that instruction are available for definition in that same instruction. Unfortunately, after this, the scavenger needs to iterate through the spill code and then visit, again, the instruction that defines the now-scavenged register. In order to avoid confusion, the register scavenger needs the ability to 'back up' through the spill code so that it can again process the instructions in the appropriate order. Prior to this fix, once the scavenger reached the just-moved instruction, it would assert if it killed any registers because, having already processed the instruction, it believed they were undefined. Unfortunately, I don't yet have a small test case. Thanks to Pranav Bhandarkar for diagnosing the problem and testing this fix. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178916 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix bug in PEI's virtual-register scavengingHal Finkel2013-04-05
| | | | | | | | | | | | | | | | | | | | This change fixes a bug that I introduced in r178058. After a register is scavenged using one of the available spills slots the instruction defining the virtual register needs to be moved to after the spill code. The scavenger has already processed the defining instruction so that registers killed by that instruction are available for definition in that same instruction. Unfortunately, after this, the scavenger needs to iterate through the spill code and then visit, again, the instruction that defines the now-scavenged register. In order to avoid confusion, the register scavenger needs the ability to 'back up' through the spill code so that it can again process the instructions in the appropriate order. Prior to this fix, once the scavenger reached the just-moved instruction, it would assert if it killed any registers because, having already processed the instruction, it believed they were undefined. Unfortunately, I don't yet have a small test case. Thanks to Pranav Bhandarkar for diagnosing the problem and testing this fix. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178845 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix target-customized spilling in the register scavengerHal Finkel2013-03-27
| | | | | | | | | | | | This is a follow-up to r178073 (which should actually make target-customized spilling work again). I still don't have a regression test for this (but it would be good to have one; Thumb 1 and Mips16 use this callback as well). Patch by Richard Sandiford. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178137 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix the register scavenger for targets that provide custom spillingHal Finkel2013-03-26
| | | | | | | | | | | As pointed out by Richard Sandiford, my recent updates to the register scavenger broke targets that use custom spilling (because the new code assumed that if there were no valid spill slots, than spilling would be impossible). I don't have a test case, but it should be possible to create one for Thumb 1, Mips 16, etc. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178073 91177308-0d34-0410-b5e6-96231b3b80d8
* Update PEI's virtual-register-based scavenging to support multiple ↵Hal Finkel2013-03-26
| | | | | | | | | | | | | | | | | | | simultaneous mappings The previous algorithm could not deal properly with scavenging multiple virtual registers because it kept only one live virtual -> physical mapping (and iterated through operands in order). Now we don't maintain a current mapping, but rather use replaceRegWith to completely remove the virtual register as soon as the mapping is established. In order to allow the register scavenger to return a physical register killed by an instruction for definition by that same instruction, we now call RS->forward(I) prior to eliminating virtual registers defined in I. This requires a minor update to forward to ignore virtual registers. These new features will be tested in forthcoming commits. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178058 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix comparison of mixed signednessHal Finkel2013-03-23
| | | | | | | | | | | 177774 broke the lld-x86_64-darwin11 builder; error: error: comparison of integers of different signs: 'int' and 'size_type' (aka 'unsigned long') for (SI = 0; SI < Scavenged.size(); ++SI) ~~ ^ ~~~~~~~~~~~~~~~~ Fix this by making SI also unsigned. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177780 91177308-0d34-0410-b5e6-96231b3b80d8
* Allow the register scavenger to spill multiple registersHal Finkel2013-03-22
| | | | | | | | | | | | | | | | | | This patch lets the register scavenger make use of multiple spill slots in order to guarantee that it will be able to provide multiple registers simultaneously. To support this, the RS's API has changed slightly: setScavengingFrameIndex / getScavengingFrameIndex have been replaced by addScavengingFrameIndex / isScavengingFrameIndex / getScavengingFrameIndices. In forthcoming commits, the PowerPC backend will use this capability in order to implement the spilling of condition registers, and some special-purpose registers, without relying on r0 being reserved. In some cases, spilling these registers requires two GPRs: one for addressing and one to hold the value being transferred. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177774 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove ScavengedRC from RegisterScavengingHal Finkel2013-03-22
| | | | | | | ScavengedRC was a dead private variable (set, but not otherwise used). No functionality change intended. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177708 91177308-0d34-0410-b5e6-96231b3b80d8
* [PEI] Pass the frame index operand number to the eliminateFrameIndex function.Chad Rosier2013-01-31
| | | | | | | Each target implementation was needlessly recomputing the index. Part of rdar://13076458 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174083 91177308-0d34-0410-b5e6-96231b3b80d8
* Use the new script to sort the includes of every file under lib.Chandler Carruth2012-12-03
| | | | | | | | | | | | | | | | | Sooooo many of these had incorrect or strange main module includes. I have manually inspected all of these, and fixed the main module include to be the nearest plausible thing I could find. If you own or care about any of these source files, I encourage you to take some time and check that these edits were sensible. I can't have broken anything (I strictly added headers, and reordered them, never removed), but they may not be the headers you'd really like to identify as containing the API being implemented. Many forward declarations and missing includes were added to a header files to allow them to parse cleanly when included first. The main module rule does in fact have its merits. =] git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169131 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove unneeded #includes.Jakub Staszak2012-11-26
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168608 91177308-0d34-0410-b5e6-96231b3b80d8
* [reg scavenger] Fix the isUsed/isAliasUsed functions so as to not report a falseChad Rosier2012-11-15
| | | | | | | | | | | | | | | | | positive. In this particular case, R6 was being spilled by the register scavenger when it was in fact dead. The isUsed function reported R6 as used because the R6_R7 alias was reserved (due to the fact that we've reserved R7 as the FP). The solution is to only check if the original register (i.e., R6) isReserved and not the aliases. The aliases are only checked to make sure they're available. The test case is derived from one of the nightly tester benchmarks and is rather intractable and difficult to reproduce, so I haven't included it. rdar://12592448 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168054 91177308-0d34-0410-b5e6-96231b3b80d8
* Switch most getReservedRegs() clients to the MRI equivalent.Jakob Stoklund Olesen2012-10-15
| | | | | | | Using the cached bit vector in MRI avoids comstantly allocating and recomputing the reserved register bit vector. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165983 91177308-0d34-0410-b5e6-96231b3b80d8
* Switch all register list clients to the new MC*Iterator interface.Jakob Stoklund Olesen2012-06-01
| | | | | | | | | | | | | No functional change intended. Sorry for the churn. The iterator classes are supposed to help avoid giant commits like this one in the future. The TableGen-produced register lists are getting quite large, and it may be necessary to change the table representation. This makes it possible to do so without changing all clients (again). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157854 91177308-0d34-0410-b5e6-96231b3b80d8
* Simplify some more getAliasSet callers.Jakob Stoklund Olesen2012-06-01
| | | | | | MCRegAliasIterator can include Reg itself in the list. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157848 91177308-0d34-0410-b5e6-96231b3b80d8
* Add an MRI::tracksLiveness() flag.Jakob Stoklund Olesen2012-03-27
| | | | | | | | | | | | | | | | | | | | Late optimization passes like branch folding and tail duplication can transform the machine code in a way that makes it expensive to keep the register liveness information up to date. There is a fuzzy line between register allocation and late scheduling where the liveness information degrades. The MRI::tracksLiveness() flag makes the line clear: While true, liveness information is accurate, and can be used for register scavenging. Once the flag is false, liveness information is not accurate, and can only be used as a hint. Late passes generally don't need the liveness information, but they will sometimes use the register scavenger to help update it. The scavenger enforces strict correctness, and we have to spend a lot of code to update register liveness that may never be used. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153511 91177308-0d34-0410-b5e6-96231b3b80d8
* Convert more GenRegisterInfo tables from unsigned to uint16_t to reduce ↵Craig Topper2012-03-05
| | | | | | static data size. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152016 91177308-0d34-0410-b5e6-96231b3b80d8
* Use uint16_t to store register overlaps to reduce static data.Craig Topper2012-03-04
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152001 91177308-0d34-0410-b5e6-96231b3b80d8
* Use uint16_t to store registers in callee saved register tables to reduce ↵Craig Topper2012-03-04
| | | | | | size of static data. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151996 91177308-0d34-0410-b5e6-96231b3b80d8
* Track reserved registers separately from RegsAvailable.Jakob Stoklund Olesen2012-02-23
| | | | | | | The bulk masking operations from register mask operands don't account for reserved registers. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151222 91177308-0d34-0410-b5e6-96231b3b80d8
* Handle regmasks in RegisterScavenging.Jakob Stoklund Olesen2012-02-22
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151210 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix some scavenger performance issues.Jakob Stoklund Olesen2012-01-29
| | | | | | | | | | | | | - Don't call malloc+free in the very hot forward(). - Don't call isTiedToDefOperand(). - Don't create BitVector temporaries. - Merge DeadRegs into KillRegs. - Eliminate the early clobber checks, they were irrelevant to scavenging. - Remove unnecessary code from -Asserts builds. This speeds up ARM PEI by 3.4x and overall llc -O0 codegen time by 11%. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149189 91177308-0d34-0410-b5e6-96231b3b80d8
* Avoid creating BitVector temporaries.Jakob Stoklund Olesen2012-01-29
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149188 91177308-0d34-0410-b5e6-96231b3b80d8
* Give better scavenger errors by invoking the verifier.Jakob Stoklund Olesen2012-01-16
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148251 91177308-0d34-0410-b5e6-96231b3b80d8
* Added a late machine instruction copy propagation pass. This catchesEvan Cheng2012-01-07
| | | | | | | | | | | | | | | | | | | | | | | | | | opportunities that only present themselves after late optimizations such as tail duplication .e.g. ## BB#1: movl %eax, %ecx movl %ecx, %eax ret The register allocator also leaves some of them around (due to false dep between copies from phi-elimination, etc.) This required some changes in codegen passes. Post-ra scheduler and the pseudo-instruction expansion passes have been moved after branch folding and tail merging. They were before branch folding before because it did not always update block livein's. That's fixed now. The pass change makes independently since we want to properly schedule instructions after branch folding / tail duplication. rdar://10428165 rdar://10640363 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147716 91177308-0d34-0410-b5e6-96231b3b80d8
* Silence a bunch (but not all) "variable written but not read" warningsDuncan Sands2011-08-12
| | | | | | | when building with assertions disabled. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137460 91177308-0d34-0410-b5e6-96231b3b80d8
* Revert "Don't check liveness of unallocatable registers."Jakob Stoklund Olesen2011-07-30
| | | | | | | The ARM target depends on CPSR liveness being tracked after register allocation. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136548 91177308-0d34-0410-b5e6-96231b3b80d8
* Don't check liveness of unallocatable registers.Jakob Stoklund Olesen2011-07-29
| | | | | | | | | | | | This includes registers like EFLAGS and ST0-ST7. We don't check for liveness issues in the verifier and scavenger because registers will never be allocated from these classes. While in SSA form, we do care about the liveness of unallocatable unreserved registers. Liveness of EFLAGS and ST0 neds to be correct for MachineDCE and MachineSinking. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136541 91177308-0d34-0410-b5e6-96231b3b80d8
* Handle <def,undef> in the second loop as well.Jakob Stoklund Olesen2011-05-02
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130718 91177308-0d34-0410-b5e6-96231b3b80d8
* Only ignore <undef> use operands, keep the <def,undef> ops.Jakob Stoklund Olesen2011-05-02
| | | | | | | | Def operands may also have an <undef> flag, but that just means that a sub-register redef doesn't actually read the super-register. For physical registers, it has no meaning. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130714 91177308-0d34-0410-b5e6-96231b3b80d8
* Add an assertion instead of crashing when the scavenger goes past the endBob Wilson2011-04-05
| | | | | | of a basic block. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128925 91177308-0d34-0410-b5e6-96231b3b80d8
* Teach the register scavenger to take subregs into account when finding a ↵Jim Grosbach2011-03-05
| | | | | | free register. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127049 91177308-0d34-0410-b5e6-96231b3b80d8
* The scavenger should just use getAllocatableSet() rather than reinventing itJim Grosbach2010-09-02
| | | | | | locally. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112845 91177308-0d34-0410-b5e6-96231b3b80d8
* Add a bit of debug output for register scavengingJim Grosbach2010-09-02
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112787 91177308-0d34-0410-b5e6-96231b3b80d8
* Simplify eliminateFrameIndex() interface back down now that PEI doesn't needJim Grosbach2010-08-26
| | | | | | to try to re-use scavenged frame index reference registers. rdar://8277890 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112241 91177308-0d34-0410-b5e6-96231b3b80d8
* Clean up scavengeRegister() a bit to prefer available regs, which allowsJim Grosbach2010-07-08
| | | | | | | | the simplification of frame index register scavenging to not have to check for available registers directly and instead just let scavengeRegister() handle it. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107880 91177308-0d34-0410-b5e6-96231b3b80d8
* When processing frame index virtual registers, consider all available registersJim Grosbach2010-07-08
| | | | | | | | | | (if there are any) and use the one which remains available for the longest rather than just using the first one. This should help enable better re-use of the loaded frame index values. rdar://7318760 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107847 91177308-0d34-0410-b5e6-96231b3b80d8
* Make post-ra scheduling, anti-dep breaking, and register scavenger ↵Evan Cheng2010-06-16
| | | | | | (conservatively) aware of predicated instructions. This enables ARM to move if-conversion before post-ra scheduler. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106091 91177308-0d34-0410-b5e6-96231b3b80d8
* Skip dbg_value instructions when scanning instructions in register scavenging.Jim Grosbach2010-06-04
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105481 91177308-0d34-0410-b5e6-96231b3b80d8
* Add argument TargetRegisterInfo to loadRegFromStackSlot and storeRegToStackSlot.Evan Cheng2010-05-06
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103193 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix PR6847. RegScavenger should ignore DebugValues.Jakob Stoklund Olesen2010-04-15
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101392 91177308-0d34-0410-b5e6-96231b3b80d8
* Eliminate MachineBasicBlock::const_livein_iterator and makeDan Gohman2010-04-13
| | | | | | | | | MachineBasicBlock::livein_iterator a const_iterator, because clients shouldn't ever be using the iterator interface to mutate the livein set. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101147 91177308-0d34-0410-b5e6-96231b3b80d8
* improve portability to avoid conflicting with std::next in c++'0x.Chris Lattner2009-12-03
| | | | | | | Patch by Howard Hinnant! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@90365 91177308-0d34-0410-b5e6-96231b3b80d8
* RegScavenger::enterBasicBlock should always reset register state.Evan Cheng2009-11-12
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86972 91177308-0d34-0410-b5e6-96231b3b80d8
* - Revert some changes from 85044, 85045, and 85047 that broke x86_64 tests andEvan Cheng2009-10-26
| | | | | | | | | | | | | | | | | | | | | | | | | | | bootstrapping. It's not safe to leave identity subreg_to_reg and insert_subreg around. - Relax register scavenging to allow use of partially "not-live" registers. It's common for targets to operate on registers where the top bits are undef. e.g. s0 = d0 = insert_subreg d0<undef>, s0, 1 ... = d0 When the insert_subreg is eliminated by the coalescer, the scavenger used to complain. The previous fix was to keep to insert_subreg around. But that's brittle and it's overly conservative when we want to use the scavenger to allocate registers. It's actually legal and desirable for other instructions to use the "undef" part of d0. e.g. s0 = d0 = insert_subreg d0<undef>, s0, 1 ... s1 = = s1 = d0 We probably need add a "partial-undef" marker on machine operand so the machine verifier would not complain. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85091 91177308-0d34-0410-b5e6-96231b3b80d8
* When the scavenger is looking for a good candidate location to restore from aJim Grosbach2009-10-25
| | | | | | | spill, it should avoid doing so inside the live range of a virtual register. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85026 91177308-0d34-0410-b5e6-96231b3b80d8
generated by cgit v1.2.3 (git 2.25.1) at 2024-06-12 12:32:30 +0000