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path: root/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp
Commit message (Expand)AuthorAge
* Rename TargetSubtarget to TargetSubtargetInfo for consistency.Evan Cheng2011-07-01
* Sink SubtargetFeature and TargetInstrItineraries (renamed MCInstrItineraries)...Evan Cheng2011-06-29
* - Rename TargetInstrDesc, TargetOperandInfo to MCInstrDesc and MCOperandInfo andEvan Cheng2011-06-28
* pre-RA-sched: Cleanup register pressure tracking.Andrew Trick2011-06-27
* The scheduler needs to be aware on the existence of untyped nodes when it per...Owen Anderson2011-06-24
* Don't allocate empty read-only SmallVectors during SelectionDAG deallocation.Benjamin Kramer2011-06-18
* Added -stress-sched flag in the Asserts build.Andrew Trick2011-06-15
* Be careful about scheduling nodes above previous calls. It increase usages ofEvan Cheng2011-04-26
* Fix a ton of comment typos found by codespell. Patch byChris Lattner2011-04-15
* In the pre-RA scheduler, maintain cmp+br proximity.Andrew Trick2011-04-14
* Recommit r129383. PreRA scheduler heuristic fixes: VRegCycle, TokenFactor lat...Andrew Trick2011-04-13
* Revert 129383. It causes some targets to hit a scheduler assert.Andrew Trick2011-04-12
* PreRA scheduler heuristic fixes: VRegCycle, TokenFactor latency.Andrew Trick2011-04-12
* Added a check in the preRA scheduler for potential interference on aAndrew Trick2011-04-07
* Improve pre-RA-sched register pressure tracking for duplicate operands.Andrew Trick2011-03-09
* Fix some latent bugs if the nodes are unschedulable. We'd gotten awayEric Christopher2011-03-08
* Fix for -sched-high-latency-cycles in sched=list-ilp mode.Andrew Trick2011-03-05
* Increased the register pressure limit on x86_64 from 8 to 12Andrew Trick2011-03-05
* Introducing a new method of tracking register pressure. We can'tAndrew Trick2011-02-04
* whitespaceAndrew Trick2011-02-03
* Reapply 124301Devang Patel2011-01-27
* Revert 124301.Devang Patel2011-01-26
* Process valid SDDbgValues even if the node does not have any order assigned.Devang Patel2011-01-26
* Refactor.Devang Patel2011-01-26
* This assertion is too restrictive, it does not apply for dangling dbg value n...Devang Patel2011-01-25
* flags -> glue for selectiondagChris Lattner2010-12-23
* rename MVT::Flag to MVT::Glue. "Flag" is a terrible name forChris Lattner2010-12-21
* Two sets of changes. Sorry they are intermingled.Evan Cheng2010-11-03
* Avoiding overly aggressive latency scheduling. If the two nodes share anEvan Cheng2010-10-29
* Re-commit 117518 and 117519 now that ARM MC test failures are out of the way.Evan Cheng2010-10-28
* Revert 117518 and 117519 for now. They changed scheduling and cause MC tests ...Evan Cheng2010-10-28
* Fix a major bug in operand latency computation. The use index must be adjustedEvan Cheng2010-10-28
* - Add TargetInstrInfo::getOperandLatency() to compute operand latencies. ThisEvan Cheng2010-10-06
* Model Cortex-a9 load to SUB, RSB, ADD, ADC, SBC, RSC, CMN, MVN, or CMPEvan Cheng2010-09-29
* Teach if-converter to be more careful with predicating instructions that wouldEvan Cheng2010-09-10
* Add missing null check reported by Amaury Pouly.Evan Cheng2010-08-10
* Fix a bug in the code which re-inserts DBG_VALUE nodes after scheduling;Dan Gohman2010-07-10
* Reapply bottom-up fast-isel, with several fixes for x86-32:Dan Gohman2010-07-10
* --- Reverse-merging r107947 into '.':Bob Wilson2010-07-09
* Re-apply bottom-up fast-isel, with fixes. Be very careful to avoid emittingDan Gohman2010-07-09
* grammar tweak in comment.Jim Grosbach2010-06-30
* Add a VT argument to getMinimalPhysRegClass and replace the copy related usesRafael Espindola2010-06-29
* Remove variables which are assigned to but for which the valueDuncan Sands2010-06-25
* It's possible that a flag is added to the SDNode that points back to theBill Wendling2010-06-24
* MorphNodeTo doesn't preserve the memory operands. Because we're morphing a nodeBill Wendling2010-06-23
* Use A.append(...) instead of A.insert(A.end(), ...) when A is aDan Gohman2010-06-21
* Code refactoring, no functionality changes.Evan Cheng2010-06-10
* Fix some latency computation bugs: if the use is not a machine opcode do not ...Evan Cheng2010-05-28
* Allow targets more controls on what nodes are scheduled by reg pressure, what...Evan Cheng2010-05-20
* Add a hybrid bottom up scheduler that reduce register usage while avoidingEvan Cheng2010-05-20