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path: root/lib/CodeGen/SelectionDAG
Commit message (Expand)AuthorAge
* Minor code cleanupsNadav Rotem2011-07-17
* LegalizeDAG doesn't need its own copy of this enum.Dan Gohman2011-07-15
* Delete LegalizeDAG's own version of isTypeLegal and getTypeActionDan Gohman2011-07-15
* Delete an unused variable and a redundant assert.Dan Gohman2011-07-15
* Modernize comments.Dan Gohman2011-07-15
* Check register class matching instead of width of type matchingEric Christopher2011-07-14
* [VECTOR-SELECT]Nadav Rotem2011-07-14
* Add assertion for the chain value typeNadav Rotem2011-07-14
* Don't emit a bit test if there is only one case the test can yield false. A s...Benjamin Kramer2011-07-14
* Add a dag combine pattern for folding C2-(A+C1) -> (C2-C1)-AEric Christopher2011-07-14
* Convert InsertValueInst and ExtractValueInst APIs to use ArrayRef.Jay Foad2011-07-13
* Add an intrinsic and codegen support for fused multiply-accumulate. The intentCameron Zwarich2011-07-08
* Apparently we can't expect a BinaryOperator here.Benjamin Kramer2011-07-08
* Emit a more efficient magic number multiplication for exact sdivs.Benjamin Kramer2011-07-08
* Remove a FIXME. All of the standard ones are in the list.Eric Christopher2011-07-07
* Add functions 'hasPredecessor' and 'hasPredecessorHelper' to SDNode. TheLang Hames2011-07-07
* Grammar and 80-col.Eric Christopher2011-07-06
* Introduce "expect" intrinsic instructions.Jakub Staszak2011-07-06
* Rename TargetSubtarget to TargetSubtargetInfo for consistency.Evan Cheng2011-07-01
* Remove getRegClassForInlineAsmConstraint and all dependencies.Eric Christopher2011-06-30
* Revert r133953 for now.Devang Patel2011-06-29
* Revert a part of r126557 which could create unschedulable DAGs.Benjamin Kramer2011-06-29
* Sink SubtargetFeature and TargetInstrItineraries (renamed MCInstrItineraries)...Evan Cheng2011-06-29
* - Rename TargetInstrDesc, TargetOperandInfo to MCInstrDesc and MCOperandInfo andEvan Cheng2011-06-28
* During bottom up fast-isel, instructions emitted to materalize registers are ...Devang Patel2011-06-27
* More refactoring. Move getRegClass from TargetOperandInfo to TargetInstrInfo.Evan Cheng2011-06-27
* The index stored in the RegDefIter is one after the current index. When gett...Owen Anderson2011-06-27
* pre-RA-sched: Cleanup register pressure tracking.Andrew Trick2011-06-27
* Distinguish early clobber output operands from clobbered registers.Jakob Stoklund Olesen2011-06-27
* The scheduler needs to be aware on the existence of untyped nodes when it per...Owen Anderson2011-06-24
* Handle debug info for i128 constants.Devang Patel2011-06-24
* Replace the existing forms of ConstantArray::get() with a single formJay Foad2011-06-22
* Fix some trailing issues from my introduction of MVT::untyped and its use for...Owen Anderson2011-06-21
* Teach dag combine to match halfword byteswap patterns.Evan Cheng2011-06-21
* Fix PromoteIntRes_TRUNCATE: Add support for cases where theNadav Rotem2011-06-20
* Code cleanups: Remove duplicated logic in PromotInteRes_BITCAST, reserve vect...Nadav Rotem2011-06-19
* Calls to AssertZext and getZeroExtendInReg must be made using scalar types.Nadav Rotem2011-06-19
* When promoting the vector elements in CopyToParts, use vector truncNadav Rotem2011-06-19
* Don't allocate empty read-only SmallVectors during SelectionDAG deallocation.Benjamin Kramer2011-06-18
* Remove unused but set variables.Benjamin Kramer2011-06-18
* Fix UMULO support for 2x register width to allow the fullEric Christopher2011-06-18
* Fix comment.Eric Christopher2011-06-17
* Lower multiply with overflow checking to __mulo<mode>Eric Christopher2011-06-17
* Don't use register classes larger than TLI->getRegClassFor(VT).Jakob Stoklund Olesen2011-06-16
* Introduce MachineBranchProbabilityInfo class, which has similar API toJakub Staszak2011-06-16
* Change the REG_SEQUENCE SDNode to take an explict register class ID as its fi...Owen Anderson2011-06-16
* Add TargetRegisterInfo::getRawAllocationOrder().Jakob Stoklund Olesen2011-06-16
* Add a DAGCombine for (ext (binop (load x), cst)).Nick Lewycky2011-06-16
* Add a new MVT::untyped. This will be used in future work for modelling ISA f...Owen Anderson2011-06-15
* Added -stress-sched flag in the Asserts build.Andrew Trick2011-06-15