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* Place this bracket according to the LLVM style.Duncan Sands2011-09-29
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140784 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove NumImplicitOps which is now unused.Jakob Stoklund Olesen2011-09-29
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140767 91177308-0d34-0410-b5e6-96231b3b80d8
* Use the local we already set up.Eric Christopher2011-09-29
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140745 91177308-0d34-0410-b5e6-96231b3b80d8
* Rewrite MachineInstr::addOperand() to avoid NumImplicitOps.Jakob Stoklund Olesen2011-09-29
| | | | | | | | | | | | | | | | | | | | | | | The function needs to scan the implicit operands anyway, so no performance is won by caching the number of implicit operands added to an instruction. This also fixes a bug when adding operands after an implicit operand has been added manually. The NumImplicitOps count wasn't kept up to date. MachineInstr::addOperand() will now consistently place all explicit operands before all the implicit operands, regardless of the order they are added. It is possible to change an MI opcode and add additional explicit operands. They will be inserted before any existing implicit operands. The only exception is inline asm instructions where operands are never reordered. This is because of a hack that marks explicit clobber regs on inline asm as <implicit-def> to please the fast register allocator. This hack can go away when InstrEmitter and FastIsel can add exact <dead> flags to physreg defs. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140744 91177308-0d34-0410-b5e6-96231b3b80d8
* Have the SjLjEHPrepare pass do some more heavy lifting.Bill Wendling2011-09-28
| | | | | | | | | Upon further review, most of the EH code should remain written at the IR level. The part which breaks SSA form is the dispatch table, so that part will be moved to the back-end. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140730 91177308-0d34-0410-b5e6-96231b3b80d8
* A typeid of zero means a cleanup, not a catch. This case occursDuncan Sands2011-09-28
| | | | | | | when there is both a catch and a cleanup. Correct the comment. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140686 91177308-0d34-0410-b5e6-96231b3b80d8
* Strip off pointer casts when looking at the eh.sjlj.functioncontext's argument.Bill Wendling2011-09-28
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140678 91177308-0d34-0410-b5e6-96231b3b80d8
* Bitcast the alloca to an i8* to match the intrinsic's signature.Bill Wendling2011-09-28
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140677 91177308-0d34-0410-b5e6-96231b3b80d8
* Create and use an llvm.eh.sjlj.functioncontext intrinsic.Bill Wendling2011-09-28
| | | | | | | | | This intrinsic is used to pass the index of the function context to the back-end for further processing. The back-end is in charge of filling in the rest of the entries. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140676 91177308-0d34-0410-b5e6-96231b3b80d8
* In the new EH model, setup the function context and the call site info.Bill Wendling2011-09-28
| | | | | | | | | | | | | The DWARF exception pass uses the call site information, which is set up here. A pre-RA pass is too late for it to use this information. So create and setup the function context here, and then insert the call site values here (and map the call sites for the DWARF EH pass). This is simpler than the original pass, and doesn't make the CFG lose its SSA-ness. It's a win-win-win-win-lose-win-win situation. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140675 91177308-0d34-0410-b5e6-96231b3b80d8
* Don't conditionalize execution of the SjLj EH prepare pass.Bill Wendling2011-09-28
| | | | | | | | We may need an SjLj EH preparation pass for some call site information, at least in the short term. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140674 91177308-0d34-0410-b5e6-96231b3b80d8
* Rename class and clean up source.Jakob Stoklund Olesen2011-09-28
| | | | | | No functional change intended. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140664 91177308-0d34-0410-b5e6-96231b3b80d8
* Rename SSEDomainFix -> lib/CodeGen/ExecutionDepsFix.Jakob Stoklund Olesen2011-09-28
| | | | | | I'll clean up the source in the next commit. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140663 91177308-0d34-0410-b5e6-96231b3b80d8
* This is the start of the new SjLj EH preparation pass, which will replace theBill Wendling2011-09-27
| | | | | | | | | | | | | | | | | | | | current IR-level pass. The old SjLj EH pass has some problems, especially with the new EH model. Most significantly, it violates some of the new restrictions the new model has. For instance, the 'dispatch' table wants to jump to the landing pad, but we cannot allow that because only an invoke's unwind edge can jump to a landing pad. This requires us to mangle the code something awful. In addition, we need to keep the now dead landingpad instructions around instead of CSE'ing them because the DWARF emitter uses that information (they are dead because no control flow edge will execute them - the control flow edge from an invoke's unwind is superceded by the edge coming from the dispatch). Basically, this pass belongs not at the IR level where SSA is king, but at the code-gen level, where we have more flexibility. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140646 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove an invalid assert that is really just asserting when the scheduler emitsCameron Zwarich2011-09-27
| | | | | | a suboptimal schedule. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140643 91177308-0d34-0410-b5e6-96231b3b80d8
* Rename AddSelectionDAGCSEId() to addSelectionDAGCSEId().Jim Grosbach2011-09-27
| | | | | | Naming conventions consistency. No functional change. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140636 91177308-0d34-0410-b5e6-96231b3b80d8
* Cleanup PromoteIntOp_EXTRACT_VECTOR_ELT and PromoteIntRes_SETCC.Nadav Rotem2011-09-27
| | | | | | | | | Add a new method: getAnyExtOrTrunc and use it to replace the manual check. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140603 91177308-0d34-0410-b5e6-96231b3b80d8
* Revert r140463; The patch assumes that <4 x i1> is saved to memory as 4 x i8,Nadav Rotem2011-09-27
| | | | | | | | while the decision is to bit-pack small values. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140601 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix emission of debug data for global variables. getContext() on ↵James Molloy2011-09-26
| | | | | | DIGlobalVariables is not valid any more. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140539 91177308-0d34-0410-b5e6-96231b3b80d8
* Add target hook for pseudo instruction expansion.Jakob Stoklund Olesen2011-09-25
| | | | | | | | | | | | Many targets use pseudo instructions to help register allocation. Like the COPY instruction, these pseudos can be expanded after register allocation. The early expansion can make life easier for PEI and the post-ra scheduler. This patch adds a hook that is called for all remaining pseudo instructions from the ExpandPostRAPseudos pass. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140472 91177308-0d34-0410-b5e6-96231b3b80d8
* [vector-select] Address one of the issues in pr10902. EXTRACT_VECTOR_ELEMENTNadav Rotem2011-09-25
| | | | | | | | | | | SDNodes may return values which are wider than the incoming element types. In this patch we fix the integer promotion of these nodes. Fixes spill-q.ll when running -promote-elements. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140471 91177308-0d34-0410-b5e6-96231b3b80d8
* Clean up code after renaming LowerSubregs -> ExpandPostRAPseudos.Jakob Stoklund Olesen2011-09-25
| | | | | | No functional change intended. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140470 91177308-0d34-0410-b5e6-96231b3b80d8
* Rename LowerSubregs to ExpandPostRAPseudos.Jakob Stoklund Olesen2011-09-25
| | | | | | | | | | | | | | I'll fix the file contents in the next commit. This pass is currently expanding the COPY and SUBREG_TO_REG pseudos. I am going to add a hook so targets can expand more pseudo-instructions after register allocation. Many targets have pseudo-instructions that assist the register allocator. They can be expanded after register allocation, before PEI and PostRA scheduling. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140469 91177308-0d34-0410-b5e6-96231b3b80d8
* Implement Duncan's suggestion to use the result of getSetCCResultType if it ↵Nadav Rotem2011-09-24
| | | | | | | | | | | | is legal (this is always the case for scalars), otherwise use the promoted result type. Fix test/CodeGen/X86/vsplit-and.ll when promote-elements is enabled. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140464 91177308-0d34-0410-b5e6-96231b3b80d8
* [Vector-Select] Address one of the problems in 10902.Nadav Rotem2011-09-24
| | | | | | | | | | | | When generating the trunc-store of i1's, we need to use the vector type and not the scalar type. This patch fixes the assertion in CodeGen/Generic/bool-vector.ll when running with -promote-elements. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140463 91177308-0d34-0410-b5e6-96231b3b80d8
* Verify that terminators follow non-terminators.Jakob Stoklund Olesen2011-09-23
| | | | | | This exposes a -segmented-stacks bug. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140429 91177308-0d34-0410-b5e6-96231b3b80d8
* PR10998: It is not legal to sink an instruction past the terminator of a ↵Eli Friedman2011-09-23
| | | | | | block; make sure we don't do that. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140428 91177308-0d34-0410-b5e6-96231b3b80d8
* Tweak the handling of MERGE_VALUES nodes: remove the need forDuncan Sands2011-09-23
| | | | | | | | | | DecomposeMERGE_VALUES to "know" that results are legalized in a particular order, by passing it the number of the result being legalized (the type legalization core provides this, it just needs to be passed on). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140373 91177308-0d34-0410-b5e6-96231b3b80d8
* Vector-Select: Address one of the problems in pr10902. Add handling for theNadav Rotem2011-09-23
| | | | | | | | | | | | integer-promotion of CONCAT_VECTORS. Test: test/CodeGen/X86/widen_shuffle-1.ll This patch fixes the above tests (when running in with -promote-elements). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140372 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix SimplifySelectCC to add newly created nodes to the DAGCombinerDan Gohman2011-09-22
| | | | | | | worklist, as it may be possible to perform further optimization on them. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140349 91177308-0d34-0410-b5e6-96231b3b80d8
* Constrain register classes instead of emitting copies.Jakob Stoklund Olesen2011-09-22
| | | | | | | | | | | Sometimes register class constraints are trivial, like GR32->GR32_NOSP, or GPR->rGPR. Teach InstrEmitter to simply constrain the virtual register instead of emitting a copy in these cases. Normally, these copies are handled by the coalescer. This saves some coalescer work. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140340 91177308-0d34-0410-b5e6-96231b3b80d8
* Add a MinNumRegs argument to MRI::constrainRegClass().Jakob Stoklund Olesen2011-09-22
| | | | | | | | | | | The function will refuse to use a register class with fewer registers than MinNumRegs. This can be used by clients to avoid accidentally increase register pressure too much. The default value of MinNumRegs=0 doesn't affect how constrainRegClass() works. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140339 91177308-0d34-0410-b5e6-96231b3b80d8
* Use the C personality function instead of the C++ personality function.Bill Wendling2011-09-22
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140318 91177308-0d34-0410-b5e6-96231b3b80d8
* Do not unnecessarily use AT_specification DIE because it does not add any value.Devang Patel2011-09-21
| | | | | | | Few weeks ago, llvm completely inverted the debug info graph. Earlier each debug info node used to keep track of its compile unit, now compile unit keeps track of important nodes. One impact of this change is that the global variable's do not have any context, which should be checked before deciding to use AT_specification DIE. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140282 91177308-0d34-0410-b5e6-96231b3b80d8
* Attempt to update the shadow stack GC pass to the new EH model.Bill Wendling2011-09-21
| | | | | | | | This inserts a cleanup landingpad instruction and a resume to mimic the old unwind instruction. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140277 91177308-0d34-0410-b5e6-96231b3b80d8
* Tidy up. Whitepsace.Jim Grosbach2011-09-21
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140275 91177308-0d34-0410-b5e6-96231b3b80d8
* [VECTOR-SELECT] Address one of the bugs in pr10902.Nadav Rotem2011-09-21
| | | | | | | | | Vector SetCC result types need to be type-legalized. This code worked before because scalar result types are known to be legal. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140249 91177308-0d34-0410-b5e6-96231b3b80d8
* Lower ARM adds/subs to add/sub after adding optional CPSR operand.Andrew Trick2011-09-21
| | | | | | | | | | | | | | This is still a hack until we can teach tblgen to generate the optional CPSR operand rather than an implicit CPSR def. But the strangeness is now limited to the selection DAG. ADD/SUB MI's no longer have implicit CPSR defs, nor do we allow flag setting variants of these opcodes in machine code. There are several corner cases to consider, and getting one wrong would previously lead to nasty miscompilation. It's not the first time I've debugged one, so this time I added enough verification to ensure it won't happen again. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140228 91177308-0d34-0410-b5e6-96231b3b80d8
* Add a DAGCombine for subvector extracts to remove useless chains ofBruno Cardoso Lopes2011-09-20
| | | | | | | subvector inserts and extracts. Initial patch by Rackover, Zvi with some tweak done by me. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140204 91177308-0d34-0410-b5e6-96231b3b80d8
* Restore hasPostISelHook tblgen flag.Andrew Trick2011-09-20
| | | | | | | | | | | No functionality change. The hook makes it explicit which patterns require "special" handling. i.e. it self-documents tblgen deficiencies. I plan to add verification in ExpandISelPseudos and Thumb2SizeReduce to catch any missing hasPostISelHooks. Otherwise it's too fragile. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140160 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM isel bug fix for adds/subs operands.Andrew Trick2011-09-20
| | | | | | | | | | | | Modified ARMISelLowering::AdjustInstrPostInstrSelection to handle the full gamut of CPSR defs/uses including instructins whose "optional" cc_out operand is not really optional. This allowed removal of the hasPostISelHook to simplify the .td files and make the implementation more robust. Fixes rdar://10137436: sqlite3 miscompile git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140134 91177308-0d34-0410-b5e6-96231b3b80d8
* whitespaceAndrew Trick2011-09-20
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140133 91177308-0d34-0410-b5e6-96231b3b80d8
* white space cleanupsNadav Rotem2011-09-18
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139994 91177308-0d34-0410-b5e6-96231b3b80d8
* Namespacify.Benjamin Kramer2011-09-16
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139892 91177308-0d34-0410-b5e6-96231b3b80d8
* Spill mode: Hoist back-copies locally.Jakob Stoklund Olesen2011-09-16
| | | | | | | | | | | | | | | | | The leaveIntvAfter() function normally inserts a back-copy after the requested instruction, making the back-copy kill the live range. In spill mode, try to insert the back-copy before the last use instead. That means the last use becomes the kill instead of the back-copy. This lowers the register pressure because the last use can now redefine the same register it was reading. This will also improve compile time: The back-copy isn't a kill, so hoisting it in hoistCopiesForSize() won't force a recomputation of the source live range. Similarly, if the back-copy isn't hoisted by the splitter, the spiller will not attempt hoisting it locally. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139883 91177308-0d34-0410-b5e6-96231b3b80d8
* Disable local spill hoisting for non-killing copies.Jakob Stoklund Olesen2011-09-16
| | | | | | | | If the source register is live after the copy being spilled, there is no point to hoisting it. Hoisting inside a basic block only serves to resolve interferences by shortening the live range of the source. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139882 91177308-0d34-0410-b5e6-96231b3b80d8
* Some legalization fixes for atomic load and store.Eli Friedman2011-09-15
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139851 91177308-0d34-0410-b5e6-96231b3b80d8
* Add an option to disable spill hoisting.Jakob Stoklund Olesen2011-09-15
| | | | | | | | When -split-spill-mode is enabled, spill hoisting is performed by SplitKit instead of by InlineSpiller. This hidden command line option is for testing the splitter spill mode. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139845 91177308-0d34-0410-b5e6-96231b3b80d8
* VirtRegMap is counting spill slots, not register spills.Jakob Stoklund Olesen2011-09-15
| | | | | | Fix the stats counters to reflect that. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139819 91177308-0d34-0410-b5e6-96231b3b80d8
* Count correctly when a COPY turns into a spill or reload.Jakob Stoklund Olesen2011-09-15
| | | | | | | The number of spills could go negative since a folded COPY is just a spill, and it may be eliminated. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139815 91177308-0d34-0410-b5e6-96231b3b80d8
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