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* Remove extraneous includes from the target machines.Eric Christopher2014-06-26
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211800 91177308-0d34-0410-b5e6-96231b3b80d8
* Move expression visitation logic up to MCStreamer.Rafael Espindola2014-06-25
| | | | | | Remove the duplicate from MCRecordStreamer. No functionality change. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211714 91177308-0d34-0410-b5e6-96231b3b80d8
* Simplify the visitation of target expressions. No functionality change.Rafael Espindola2014-06-25
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211707 91177308-0d34-0410-b5e6-96231b3b80d8
* Resubmit commit r211533Weiming Zhao2014-06-24
| | | | | | | | | "Fix PR20056: Implement pseudo LDR <reg>, =<literal/label> for AArch64" Missed files are added in this commit. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211605 91177308-0d34-0410-b5e6-96231b3b80d8
* This reverts commit r211533 and r211539.Rafael Espindola2014-06-23
| | | | | | | | | Revert "Fix PR20056: Implement pseudo LDR <reg>, =<literal/label> for AArch64" Revert "Fix cmake build." It was missing a file. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211540 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix cmake build.Juergen Ributzka2014-06-23
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211539 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix PR20056: Implement pseudo LDR <reg>, =<literal/label> for AArch64Weiming Zhao2014-06-23
| | | | | | | | | | | | | | | | | | | | This patch is based on the changes from ARM target [1,2] Based on ARM doc [3], if the literal value can be loaded with a valid MOV, it can emit that instruction. This is implemented in this patch. [1] Fix PR18345: ldr= pseudo instruction produces incorrect code when using in inline assembly Author: David Peixotto <dpeixott@codeaurora.org> commit b92cca222898d87bbc764fa22e805adb04ef7f13 (r200777) [2] Implement the ldr-pseudo opcode for ARM assembly Author: David Peixotto <dpeixott@codeaurora.org> commit 0fa193b08627927ccaa0804a34d80480894614b8 (r197708) [3] http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dui0802a/CJAHAIBC.html Differential Revision: http://reviews.llvm.org/D4163 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211533 91177308-0d34-0410-b5e6-96231b3b80d8
* Convert some assert(0) to llvm_unreachable or fold an 'if' condition into ↵Craig Topper2014-06-19
| | | | | | the assert. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211254 91177308-0d34-0410-b5e6-96231b3b80d8
* [AArch64] Fix a pattern match failure caused by creating improper CONCAT_VECTOR.Kevin Qin2014-06-18
| | | | | | | | | ReconstructShuffle() may wrongly creat a CONCAT_VECTOR trying to concat 2 of v2i32 into v4i16. This commit is to fix this issue and try to generate UZP1 instead of lots of MOV and INS. Patch is initalized by Kevin Qin, and refactored by Tim Northover. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211144 91177308-0d34-0410-b5e6-96231b3b80d8
* Replace some assert(0)'s with llvm_unreachable.Craig Topper2014-06-18
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211141 91177308-0d34-0410-b5e6-96231b3b80d8
* AArch64: estimate inline asm length during branch relaxationTim Northover2014-06-17
| | | | | | | | | | | | | To make sure branches are in range, we need to do a better job of estimating the length of an inline assembly block than "it's probably 1 instruction, who'd write asm with more than that?". Fortunately there's already a (highly suspect, see how many ways you can think of to break it!) callback for this purpose, which is used by the other targets. rdar://problem/17277590 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211095 91177308-0d34-0410-b5e6-96231b3b80d8
* AArch64: Add backend intrinsic for rbit.Jim Grosbach2014-06-16
| | | | | | | | | Define an intrinsic for the frontend to use and pattern match it to the RBIT instruction. rdar://9283021 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211058 91177308-0d34-0410-b5e6-96231b3b80d8
* [AArch64] Remove dead code.Tilmann Scheller2014-06-16
| | | | | | Both function declarations lack a callee and an implementation. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211029 91177308-0d34-0410-b5e6-96231b3b80d8
* [AArch64] Fix a fencepost error in lowering for llvm.aarch64.neon.uqshl.James Molloy2014-06-16
| | | | | | | | Patch by Jiangning Liu! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211014 91177308-0d34-0410-b5e6-96231b3b80d8
* AArch64: improve handling & modelling of FP_TO_XINT nodes.Tim Northover2014-06-15
| | | | | | | | There's probably no acatual change in behaviour here, just updating the LowerFP_TO_INT function to be more similar to the reverse implementation and updating costs to current CodeGen. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210985 91177308-0d34-0410-b5e6-96231b3b80d8
* AArch64: improve vector [su]itofp handling.Tim Northover2014-06-15
| | | | | | | This somehow got missed in the AArch64 merge, so should fix a performance regression since 3.4. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210984 91177308-0d34-0410-b5e6-96231b3b80d8
* [AArch64] Basic Sched Model for Cortex-A57.Chad Rosier2014-06-11
| | | | | | | Patch by Dave Estes<cestes@codeaurora.org> Differential Revision: http://reviews.llvm.org/D4008 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210705 91177308-0d34-0410-b5e6-96231b3b80d8
* Move to a private function to initialize the subtarget dependenciesEric Christopher2014-06-11
| | | | | | so that we can use initializer lists for the AArch64 Subtarget. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210616 91177308-0d34-0410-b5e6-96231b3b80d8
* Move AArch64TargetLowering to AArch64Subtarget.Eric Christopher2014-06-10
| | | | | | | This currently necessitates a TargetMachine for the TargetLowering constructor and TLOF. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210605 91177308-0d34-0410-b5e6-96231b3b80d8
* Move AArch64InstrInfo to AArch64Subtarget.Eric Christopher2014-06-10
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210599 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove a method that was just replacing direct access to a member.Eric Christopher2014-06-10
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210598 91177308-0d34-0410-b5e6-96231b3b80d8
* Move AArch64SelectionDAGInfo down to the subtarget.Eric Christopher2014-06-10
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210557 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove the cached little endian variable. We can get it easily offEric Christopher2014-06-10
| | | | | | of the DataLayout. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210555 91177308-0d34-0410-b5e6-96231b3b80d8
* Have AArch64SelectionDAGInfo take a DataLayout parameter ratherEric Christopher2014-06-10
| | | | | | than a TargetMachine. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210554 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove caching of the subtarget for AArch64SelectionDAGInfo.Eric Christopher2014-06-10
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210553 91177308-0d34-0410-b5e6-96231b3b80d8
* Move DataLayout onto the AArch64 subtarget.Eric Christopher2014-06-10
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210552 91177308-0d34-0410-b5e6-96231b3b80d8
* Move AArch64FrameLowering into the subtarget.Eric Christopher2014-06-10
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210549 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove the uses of AArch64TargetMachine and AArch64Subtarget fromEric Christopher2014-06-10
| | | | | | AArch64FrameLowering. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210548 91177308-0d34-0410-b5e6-96231b3b80d8
* [AArch64] Emit .ident compiler version attribute.Chad Rosier2014-06-10
| | | | | | Patch by Ana Pazos<apazos@codeaurora.org>! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210535 91177308-0d34-0410-b5e6-96231b3b80d8
* Condition codes AL and NV are invalid in the aliases that useArtyom Skrobov2014-06-10
| | | | | | | | | | | | | | | | inverted condition codes (CINC, CINV, CNEG, CSET, and CSETM). Matching aliases based on "immediate classes", when disassembling, wasn't previously supported, hence adding MCOperandPredicate into class Operand, and implementing the support for it in AsmWriterEmitter. The parsing for those aliases was already custom, so just adding the missing condition into AArch64AsmParser::parseCondCode. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210528 91177308-0d34-0410-b5e6-96231b3b80d8
* AArch64: disallow x30 & x29 as the destination for indirect tail callsTim Northover2014-06-10
| | | | | | | | As Ana Pazos pointed out, these have to be restored to their incoming values before a function returns; i.e. before the tail call. So they can't be used correctly as the destination register. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210525 91177308-0d34-0410-b5e6-96231b3b80d8
* AArch64: teach FastISel how to handle offset FrameIndicesTim Northover2014-06-10
| | | | | | | | | | Previously we were abandonning the attempt, leading to some combination of extra work (when selection of a load/store fails completely) and inferior code (when this leads to a real memcpy call instead of inlining). rdar://problem/17187463 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210520 91177308-0d34-0410-b5e6-96231b3b80d8
* AArch64: make FastISel memcpy emission more robust.Tim Northover2014-06-10
| | | | | | | | | | We were hitting an assert if FastISel couldn't create the load or store we requested. Currently this happens for large frame-local addresses, though CodeGen could be improved there. rdar://problem/17187463 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210519 91177308-0d34-0410-b5e6-96231b3b80d8
* [AArch64] Missing aliases for CMP/CMN [W]SP with no shiftArtyom Skrobov2014-06-09
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210464 91177308-0d34-0410-b5e6-96231b3b80d8
* [AArch64] Fix the ordering of the accumulate operand in SchedRW list.Chad Rosier2014-06-09
| | | | | | | Patch by Dave Estes <cestes@codeaurora.org> http://reviews.llvm.org/D4037 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210446 91177308-0d34-0410-b5e6-96231b3b80d8
* [AArch64] When combining constant mul of power of 2 plus/minus 1, prefer shiftChad Rosier2014-06-09
| | | | | | | plus add. The shift can be folded into the add. This only effects codegen when the constant is 3. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210445 91177308-0d34-0410-b5e6-96231b3b80d8
* [C++11] Use 'nullptr'.Craig Topper2014-06-08
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210442 91177308-0d34-0410-b5e6-96231b3b80d8
* AsmMatchers: Use unique_ptr to manage ownership of MCParsedAsmOperandDavid Blaikie2014-06-08
| | | | | | | | | | | | I saw at least a memory leak or two from inspection (on probably untested error paths) and r206991, which was the original inspiration for this change. I ran this idea by Jim Grosbach a few weeks ago & he was OK with it. Since it's a basically mechanical patch that seemed sufficient - usual post-commit review, revert, etc, as needed. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210427 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove outdated CMake MSVC workaroundAlp Toker2014-06-08
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210421 91177308-0d34-0410-b5e6-96231b3b80d8
* Have TargetSelectionDAGInfo take a DataLayout initializer rather thanEric Christopher2014-06-06
| | | | | | a TargetMachine since the only thing it wants is DataLayout. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210366 91177308-0d34-0410-b5e6-96231b3b80d8
* [AArch64] clang-format the load/store optimizer.Tilmann Scheller2014-06-04
| | | | | | No change in functionality. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210182 91177308-0d34-0410-b5e6-96231b3b80d8
* [AArch64] Fix some LLVM Coding Standards violations in the load/store optimizer.Tilmann Scheller2014-06-04
| | | | | | | | Variable names should start with an upper case letter. No change in functionality. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210181 91177308-0d34-0410-b5e6-96231b3b80d8
* [AArch64] Fix typo in load/store optimizer.Tilmann Scheller2014-06-03
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210114 91177308-0d34-0410-b5e6-96231b3b80d8
* AArch64: mark small types (i1, i8, i16) as promotedTim Northover2014-06-03
| | | | | | | | | This means the output of LowerFormalArguments returns a lowered SDValue with the correct type (expected in SelectionDAGBuilder). Without this, an assertion under a DEBUG macro triggers when those types are passed on the stack. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210102 91177308-0d34-0410-b5e6-96231b3b80d8
* [AArch64] Correctly deal with VPR stack parameter passing.Jiangning Liu2014-06-03
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210067 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix typosAlp Toker2014-05-31
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209982 91177308-0d34-0410-b5e6-96231b3b80d8
* Have the TLOF creation take a Triple rather than needing a subtarget.Eric Christopher2014-05-31
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209937 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM & AArch64: make use of common cmpxchg idioms after expansionTim Northover2014-05-30
| | | | | | | | | | | | | | | | | | | | | | | | The C and C++ semantics for compare_exchange require it to return a bool indicating success. This gets mapped to LLVM IR which follows each cmpxchg with an icmp of the value loaded against the desired value. When lowered to ldxr/stxr loops, this extra comparison is redundant: its results are implicit in the control-flow of the function. This commit makes two changes: it replaces that icmp with appropriate PHI nodes, and then makes sure earlyCSE is called after expansion to actually make use of the opportunities revealed. I've also added -{arm,aarch64}-enable-atomic-tidy options, so that existing fragile tests aren't perturbed too much by the change. Many of them either rely on undef/unreachable too pervasively to be restored to something well-defined (particularly while making sure they test the same obscure assert from many years ago), or depend on a particular CFG shape, which is disrupted by SimplifyCFG. rdar://problem/16227836 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209883 91177308-0d34-0410-b5e6-96231b3b80d8
* Restore getInvertedCondCode() from the phased-out backend, fixing ↵Artyom Skrobov2014-05-29
| | | | | | disassembly for NV git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209803 91177308-0d34-0410-b5e6-96231b3b80d8
* Add missing check when MatchInstructionImpl() reports failureArtyom Skrobov2014-05-29
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209802 91177308-0d34-0410-b5e6-96231b3b80d8
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