| Commit message (Expand) | Author | Age |
* | Split up the ARM so_reg ComplexPattern into so_reg_reg and so_reg_imm, allowi... | Owen Anderson | 2011-07-21 |
* | Sink ARMMCExpr and ARMAddressingModes into MC layer. First step to separate A... | Evan Cheng | 2011-07-20 |
* | Remove VMOVDneon and VMOVQ, which are just aliases for VORR. This continues ... | Owen Anderson | 2011-07-15 |
* | Next round of MC refactoring. This patch factor MC table instantiations, MC | Evan Cheng | 2011-07-14 |
* | Add a target-indepedent entry to MCInstrDesc to describe the encoded size of ... | Owen Anderson | 2011-07-13 |
* | Use BranchProbability instead of floating points in IfConverter. | Jakub Staszak | 2011-07-10 |
* | Hide the call to InitMCInstrInfo into tblgen generated ctor. | Evan Cheng | 2011-07-01 |
* | Refactor away tSpill and tRestore pseudos in ARM backend. | Jim Grosbach | 2011-06-29 |
* | Move CallFrameSetupOpcode and CallFrameDestroyOpcode to TargetInstrInfo. | Evan Cheng | 2011-06-28 |
* | Merge XXXGenRegisterNames.inc into XXXGenRegisterInfo.inc | Evan Cheng | 2011-06-28 |
* | - Rename TargetInstrDesc, TargetOperandInfo to MCInstrDesc and MCOperandInfo and | Evan Cheng | 2011-06-28 |
* | use the MachineInstrBuilder operator-> to simplify some code. | Chris Lattner | 2011-04-29 |
* | Change A9 scheduling itineraries VLD* / VST* entries default to "aligned". That | Evan Cheng | 2011-04-19 |
* | Add ORR and EOR to the CMP peephole optimizer. It's hard to get isel to generate | Cameron Zwarich | 2011-04-15 |
* | The AND instruction leaves the V flag unmodified, so it falls victim to the same | Cameron Zwarich | 2011-04-15 |
* | Add missing register forms of instructions to the ARM CMP-folding code. This | Cameron Zwarich | 2011-04-15 |
* | Fix a ton of comment typos found by codespell. Patch by | Chris Lattner | 2011-04-15 |
* | Fix a typo. | Cameron Zwarich | 2011-04-13 |
* | Teach the ARM peephole optimizer that RSB, RSC, ADC, and SBC can be used for ... | Owen Anderson | 2011-04-06 |
* | Get rid of the non-writeback versions VLDMDB and VSTMDB, which don't actually... | Owen Anderson | 2011-03-29 |
* | Nasty bug in ARMBaseInstrInfo::produceSameValue(). The MachineConstantPoolEntry | Evan Cheng | 2011-03-24 |
* | Cmp peephole optimization isn't always safe for signed arithmetics. | Evan Cheng | 2011-03-23 |
* | Preliminary support for ARM frame save directives emission via MI flags. | Anton Korobeynikov | 2011-03-05 |
* | Last round of fixes for movw + movt global address codegen. | Evan Cheng | 2011-01-21 |
* | Convert -enable-sched-cycles and -enable-sched-hazard to -disable | Andrew Trick | 2011-01-21 |
* | Don't be overly aggressive with CSE of "ldr constantpool". If it's a pc-relative | Evan Cheng | 2011-01-20 |
* | Sorry, several patches in one. | Evan Cheng | 2011-01-20 |
* | Materialize GA addresses with movw + movt pairs for Darwin in PIC mode. e.g. | Evan Cheng | 2011-01-17 |
* | Simplify a bunch of isVirtualRegister() and isPhysicalRegister() logic. | Jakob Stoklund Olesen | 2011-01-10 |
* | Recognize inline asm 'rev /bin/bash, ' as a bswap intrinsic call. | Evan Cheng | 2011-01-08 |
* | Various bits of framework needed for precise machine-level selection | Andrew Trick | 2010-12-24 |
* | whitespace | Andrew Trick | 2010-12-24 |
* | Remove the rest of the *_sfp Neon instruction patterns. | Bob Wilson | 2010-12-13 |
* | Refactor the ARM CMPz* patterns to just use the normal CMP instructions when | Jim Grosbach | 2010-12-07 |
* | Making use of VFP / NEON floating point multiply-accumulate / subtraction is | Evan Cheng | 2010-12-05 |
* | Rename t2 TBB and TBH instructions to reference that they encode the jump table | Jim Grosbach | 2010-11-29 |
* | Move callee-saved regs spills / reloads to TFI | Anton Korobeynikov | 2010-11-27 |
* | Rewrite stack callee saved spills and restores to use push/pop instructions. | Eric Christopher | 2010-11-18 |
* | Silence compiler warnings. | Evan Cheng | 2010-11-18 |
* | Remove ARM isel hacks that fold large immediates into a pair of add, sub, and, | Evan Cheng | 2010-11-17 |
* | Simplify code that toggle optional operand to ARM::CPSR. | Evan Cheng | 2010-11-17 |
* | Encode the multi-load/store instructions with their respective modes ('ia', | Bill Wendling | 2010-11-16 |
* | Code clean up. The peephole pass should be the one updating the instruction | Evan Cheng | 2010-11-15 |
* | Revert this temporarily. | Eric Christopher | 2010-11-11 |
* | Change the prologue and epilogue to use push/pop for the low ARM registers. | Eric Christopher | 2010-11-11 |
* | Two sets of changes. Sorry they are intermingled. | Evan Cheng | 2010-11-03 |
* | When we look at instructions to convert to setting the 's' flag, we need to look | Bill Wendling | 2010-11-01 |
* | Fix fpscr <-> GPR latency info. | Evan Cheng | 2010-10-29 |
* | Avoiding overly aggressive latency scheduling. If the two nodes share an | Evan Cheng | 2010-10-29 |
* | Re-commit 117518 and 117519 now that ARM MC test failures are out of the way. | Evan Cheng | 2010-10-28 |