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path: root/lib/Target/ARM/ARMISelDAGToDAG.cpp
Commit message (Expand)AuthorAge
* Fix known typosAlp Toker2014-01-24
* ARM: use litpools for normal i32 imms when compiling minsize.Tim Northover2014-01-23
* For ARM, fix assertuib failures for some ld/st 3/4 instruction with wirteback.Jiangning Liu2014-01-16
* ARM: add pseudo-instructions for lit-pool global materialisationTim Northover2013-12-02
* [ARM] Use the load-acquire/store-release instructions optimally in AArch32.Amara Emerson2013-09-26
* ISelDAG: spot chain cycles involving MachineNodesTim Northover2013-09-22
* ARM: use TableGen patterns to select CMOV operations.Tim Northover2013-08-22
* ARM: make sure we keep inline asm operands tied.Tim Northover2013-08-18
* Allow generation of vmla.f32 instructions when targeting Cortex-A15. The patc...Silviu Baranga2013-07-29
* ARM: implement ldrex, strex and clrex intrinsicsTim Northover2013-07-16
* Add a comment to this change, requested by Eric Christopher.Joey Gouly2013-07-08
* PR16490: fix a crash in ARMDAGToDAGISel::SelectInlineAsm.Joey Gouly2013-07-05
* Remove unused variables.Eric Christopher2013-06-28
* Bug 13662: Enable GPRPair for all i64 operands of inline asm on ARMWeiming Zhao2013-06-28
* Access the TargetLoweringInfo from the TargetMachine object instead of cachin...Bill Wendling2013-06-19
* Cache the TargetLowering info object as a pointer.Bill Wendling2013-06-06
* Track IR ordering of SelectionDAG nodes 2/4.Andrew Trick2013-05-25
* Replace Count{Leading,Trailing}Zeros_{32,64} with count{Leading,Trailing}Zeros.Michael J. Spencer2013-05-24
* ArrayRefize getMachineNode(). No functionality change.Michael Liao2013-04-19
* Don't glue users to extract_subreg when selecting the llvm.arm.ldrexdLang Hames2013-03-09
* ArrayRefize some code. No functionality change.Benjamin Kramer2013-03-07
* Re-apply r175088 for bug fix 13622: Add paired register support forWeiming Zhao2013-02-14
* temporarily revert the patch due to some conflictsWeiming Zhao2013-02-13
* Bug fix 13622: Add paired register support for inline asm with 64-bit data on...Weiming Zhao2013-02-13
* Move all of the header files which are involved in modelling the LLVM IRChandler Carruth2013-01-02
* LLVM sdisel normalize bit extraction of the form:Evan Cheng2012-12-19
* Use the new script to sort the includes of every file under lib.Chandler Carruth2012-12-03
* Added atomic 64 min/max/umin/umax instrinsics support in the ARM backend.Silviu Baranga2012-11-29
* Rename methods like PairSRegs() to createSRegpairNode() to meet our codingWeiming Zhao2012-11-17
* Remove hard coded registers in ARM ldrexd and strexd instructionsWeiming Zhao2012-11-16
* Add LLVM support for Swift.Bob Wilson2012-09-29
* Revert 'Fix a typo 'iff' => 'if''. iff is an abreviation of if and only if. S...Sylvestre Ledru2012-09-27
* Fix a typo 'iff' => 'if'Sylvestre Ledru2012-09-27
* Fix Doxygen issues:Dmitri Gribenko2012-09-14
* This patch introduces A15 as a target in LLVM.Silviu Baranga2012-09-13
* Patch to implement UMLAL/SMLAL instructions for the ARM architectureArnold Schwaighofer2012-09-04
* Remove the CAND/COR/CXOR custom ISD nodes and their select code.Jakob Stoklund Olesen2012-08-18
* Add missing Rfalse operand to the predicated pseudo-instructions.Jakob Stoklund Olesen2012-08-15
* Revert 161581: Patch to implement UMLAL/SMLAL instructions for the ARMArnold Schwaighofer2012-08-12
* Patch to implement UMLAL/SMLAL instructions for the ARM architectureArnold Schwaighofer2012-08-09
* Clean up formatting.Jim Grosbach2012-08-01
* Tidy up.Jim Grosbach2012-08-01
* Make some opcode tables static and const. Allows code to avoid making copies ...Craig Topper2012-05-24
* Test commit.Tim Northover2012-04-26
* ARM 'vuzp.32 Dd, Dm' is a pseudo-instruction.Jim Grosbach2012-04-11
* ARM 'vzip.32 Dd, Dm' is a pseudo-instruction.Jim Grosbach2012-04-11
* ARM refactor more NEON VLD/VST instructions to use composite physregsJim Grosbach2012-03-06
* ARM refactor away a bunch of VLD/VST pseudo instructions.Jim Grosbach2012-03-05
* Remove unused variable.Duncan Sands2012-02-23
* Optimize a couple of common patterns involving conditional moves where the falseEvan Cheng2012-02-23