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ARM
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Disassembler
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ARMDisassembler.cpp
Commit message (
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Author
Age
...
*
Remove unused variable
Matt Beaumont-Gay
2011-11-30
*
ARM parsing for VLD1 all lanes, with writeback.
Jim Grosbach
2011-11-30
*
ARM assembly parsing and encoding for four-register VST1.
Jim Grosbach
2011-11-29
*
ARM assembly parsing and encoding for three-register VST1.
Jim Grosbach
2011-11-29
*
Fix a misplaced paren bug.
Owen Anderson
2011-11-15
*
Fix an ambiguous decoding where we failed to properly decode VMOVv2f32 and VM...
Owen Anderson
2011-11-15
*
Re-apply 144430, this time with the associated isel and disassmbler bits.
Jim Grosbach
2011-11-12
*
Remove the unnecessary dependency on libARMCodeGen from libARMDisassembler.
Benjamin Kramer
2011-11-11
*
The rules disallowing single-register reglist operands only apply to the POP ...
Owen Anderson
2011-11-02
*
Register list operands are not allowed to contain only a single register. Al...
Owen Anderson
2011-11-02
*
Fix disassembly of some VST1 instructions.
Owen Anderson
2011-11-01
*
ARM VST1 w/ writeback assembly parsing and encoding.
Jim Grosbach
2011-10-31
*
More not-crashing NEON disassembly updates for the vld refactoring.
Owen Anderson
2011-10-31
*
Reapply r143202, with a manual decoding hook for SWP. This change inadvertan...
Owen Anderson
2011-10-28
*
Add some NEON stores to the VLD decoding hook that were accidentally omitted ...
Owen Anderson
2011-10-27
*
ARM assembly parsing and encoding for VLD1 with writeback.
Jim Grosbach
2011-10-25
*
ARM assembly parsing and encoding for VLD1 w/ writeback.
Jim Grosbach
2011-10-24
*
ARM refactor am6offset usage for VLD1.
Jim Grosbach
2011-10-24
*
Fix a NEON disassembly case that was broken in the recent refactorings. As m...
Owen Anderson
2011-10-24
*
Move various generated tables into read-only memory, fixing up const correctn...
Benjamin Kramer
2011-10-22
*
Assembly parsing for 4-register sequential variant of VLD2.
Jim Grosbach
2011-10-21
*
Assembly parsing for 2-register sequential variant of VLD2.
Jim Grosbach
2011-10-21
*
Assembly parsing for 4-register variant of VLD1.
Jim Grosbach
2011-10-21
*
Assembly parsing for 3-register variant of VLD1.
Jim Grosbach
2011-10-21
*
ARM VLD parsing and encoding.
Jim Grosbach
2011-10-21
*
Tidy up. Trailing whitespace.
Jim Grosbach
2011-10-20
*
Removed set, but unused variables.
Chad Rosier
2011-10-17
*
Fix a non-firing assert. Change:
Richard Trieu
2011-10-14
*
Fix undefined shift. Patch by Ahmed Charles.
Eli Friedman
2011-10-13
*
SETEND is not allowed in an IT block.
Owen Anderson
2011-10-13
*
ARM addrmode5 represents the 'U' bit of the encoding backwards.
Jim Grosbach
2011-10-12
*
Thumb2 assembly parsing and encoding for LDC/STC.
Jim Grosbach
2011-10-12
*
addrmode2 is gone from these, so no need for the reg0 operand.
Jim Grosbach
2011-10-12
*
Fix the check for nested IT instructions in the disassembler. We need to per...
Owen Anderson
2011-10-06
*
Adding back support for printing operands symbolically to ARM's new disassembler
Kevin Enderby
2011-10-04
*
ARM fix encoding of VMOV.f32 and VMOV.f64 immediates.
Jim Grosbach
2011-09-30
*
ASR #32 is not allowed on Thumb2 USAT and SSAT instructions.
Owen Anderson
2011-09-26
*
Reapply r140412 (Thumb2 reg-reg loads cannot target SP or PC), with invalid t...
Owen Anderson
2011-09-23
*
Revert r140412. This affects more instructions than intended.
Owen Anderson
2011-09-23
*
Thumb2 register-shifted-register loads cannot target the PC or the SP.
Owen Anderson
2011-09-23
*
tMOVSr is not allowed in an IT block either.
Owen Anderson
2011-09-19
*
CPS instructions are UNPREDICTABLE inside IT blocks.
Owen Anderson
2011-09-19
*
Thumb2 TBB and TBH instructions are only allowed at the end of IT blocks, not...
Owen Anderson
2011-09-19
*
Thumb2 assembly parsing and encoding for TBB/TBH.
Jim Grosbach
2011-09-19
*
Handle STRT (and friends) like LDRT (and friends) for decoding purposes. Por...
Owen Anderson
2011-09-19
*
Bitfield mask instructions are unpredictable if the encoded LSB is higher tha...
Owen Anderson
2011-09-16
*
Fix bitfield decoding based on Eli's feedback.
Owen Anderson
2011-09-16
*
Thumb2 pre-indexed loads/stores use the restricted GPR set for Rt.
Owen Anderson
2011-09-16
*
Fix disassembly of Thumb2 BFI instructions with bit range of [0, 32).
Owen Anderson
2011-09-16
*
Fix disassembly of Thumb2 LDRSH with a #-0 offset.
Owen Anderson
2011-09-16
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