summaryrefslogtreecommitdiff
path: root/lib/Target/Mips/Mips64InstrInfo.td
Commit message (Collapse)AuthorAge
...
* [mips] Resolve register classes dynamically using ptr_rc to reduce the number ofAkira Hatanaka2013-08-20
| | | | | | | | | | load/store instructions defined. Previously, we were defining load/store instructions for each pointer size (32 and 64-bit), but now we need just one definition. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188830 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips] Rename HIRegs and LORegs.Akira Hatanaka2013-08-14
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188341 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips] Rename accumulator register classes and FP register operands.Akira Hatanaka2013-08-08
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188020 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips] Delete register class HWRegs64.Akira Hatanaka2013-08-08
| | | | | | | No functionality change. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188016 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips] Rename register classes CPURegs and CPU64Regs.Akira Hatanaka2013-08-06
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187832 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips] Mark instructions defined in Mips64InstrInfo.td that are duplicates ofAkira Hatanaka2013-08-06
| | | | | | | instructions defined in MipsInstrInfo.td as codegen-only instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187828 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips] Delete unnecessary InstAliases. Also, clear some of the InstAlias'Akira Hatanaka2013-08-06
| | | | | | | EmitAlias flag and have MipsInstPrinter::printAlias print the aliases. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187824 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips] Replace usages of register classes with register operands. Also, removeAkira Hatanaka2013-08-06
| | | | | | | | unnecessary jalr InstAliases in Mips64InstrInfo.td and add the code to print jalr InstAliases in MipsInstPrinter::printAlias. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187821 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips] Make load/store accumulator pseudo instructions codeGenOnly. Also,Akira Hatanaka2013-08-01
| | | | | | | | | remove lines that are setting DecoderNamespace for pseudo atomic instructions. No intended functionality change. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187632 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips] Rename instruction DANDi to ANDi64.Akira Hatanaka2013-07-31
| | | | | | | No functionality change. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187469 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips] Define instruction itineraries IIArith and IILogic.Akira Hatanaka2013-07-31
| | | | | | | No functionality change. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187468 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips] Use ADDu instead of OR to copy general purpose registers. Also, deleteAkira Hatanaka2013-07-22
| | | | | | | | | the InstAlias pattern which maps "move" to OR to resolve ambiguity in MatchTable. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186855 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips] Add instruction itinerary classes for mult, seb and slt instructions.Akira Hatanaka2013-07-12
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186222 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips] Add new InstrItinClasses for move from/to coprocessor instructions andAkira Hatanaka2013-07-02
| | | | | | | | | floating point loads and stores. No changes in functionality. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185399 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips] Add instruction selection patterns for blez and bgez.Akira Hatanaka2013-05-21
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182396 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips] Trap on integer division by zero.Akira Hatanaka2013-05-20
| | | | | | | | | By default, a teq instruction is inserted after integer divide. No divide-by-zero checks are performed if option "-mnocheck-zero-division" is used. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182306 91177308-0d34-0410-b5e6-96231b3b80d8
* Mips assembler: Add branch macro definitionsJack Carter2013-05-16
| | | | | | | | | | | | | This patch adds bnez and beqz instructions which represent alias definitions for bne and beq instructions as follows: bnez $rs,$imm => bne $rs,$zero,$imm beqz $rs,$imm => beq $rs,$zero,$imm The corresponding test cases are added. Patch by Vladimir Medic git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182040 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips] Fix handling of instructions which copy to/from accumulator registers.Akira Hatanaka2013-04-30
| | | | | | | | | | | Expand copy instructions between two accumulator registers before callee-saved scan is done. Handle copies between integer GPR and hi/lo registers in MipsSEInstrInfo::copyPhysReg. Delete pseudo-copy instructions that are not needed. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180827 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips] Fix definitions of multiply, multiply-add/sub and divide instructions.Akira Hatanaka2013-03-30
| | | | | | | | | | The new instructions have explicit register output operands and use table-gen patterns instead of C++ code to do instruction selection. Mips16's instructions are unaffected by this change. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178403 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips] Define pseudo instructions for spilling and copying accumulatorAkira Hatanaka2013-03-30
| | | | | | | registers. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178390 91177308-0d34-0410-b5e6-96231b3b80d8
* [Mips Assembler] Add support for OR macro with imediate opperandJack Carter2013-03-28
| | | | | | | | | | | Mips assembler supports macros that allows the OR instruction to have an immediate parameter. This patch adds an instruction alias that converts this macro into a Mips ORI instruction. Contributer: Vladimir Medic git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178316 91177308-0d34-0410-b5e6-96231b3b80d8
* [Mips Assembler] Add alias definitions for jalJack Carter2013-03-28
| | | | | | | | | | | | | Mips assembler allows following to be used as aliased instructions: jal $rs for jalr $rs jal $rd,$rd for jalr $rd,$rs This patch provides alias definitions in td files and test cases to show the usage. Contributer: Vladimir Medic git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178304 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips] Print move instructions.Akira Hatanaka2013-03-04
| | | | | | | | "move $4, $5" is printed instead of "or $4, $5, $zero". git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176455 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips] Add definition of JALR instruction which has two register operands. ↵Akira Hatanaka2013-02-07
| | | | | | | | | | Change the original JALR instruction with one register operand to be a pseudo-instruction. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174657 91177308-0d34-0410-b5e6-96231b3b80d8
* This patch that sets the EmitAlias flag in td files Jack Carter2013-02-05
| | | | | | | | | | | | | | | and enables the instruction printer to print aliased instructions. Due to usage of RegisterOperands a change in common code (utils/TableGen/AsmWriterEmitter.cpp) is required to get the correct register value if it is a RegisterOperand. Contributer: Vladimir Medic git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174358 91177308-0d34-0410-b5e6-96231b3b80d8
* This is a resubmittal. For some reason it broke the bots yesterdayJack Carter2013-01-18
| | | | | | | | | | | | | but I cannot reproduce the problem and have scrubed my sources and even tested with llvm-lit -v --vg. Removal of redundant code and formatting fixes. Contributers: Jack Carter/Vladimir Medic git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172842 91177308-0d34-0410-b5e6-96231b3b80d8
* This patch tackles the problem of parsing Mips Jack Carter2013-01-12
| | | | | | | | | | | | | | | | | | | | register names in the standalone assembler llvm-mc. Registers such as $A1 can represent either a 32 or 64 bit register based on the instruction using it. In addition, based on the abi, $T0 can represent different 32 bit registers. The problem is resolved by the Mips specific AsmParser td definitions changing to work together. Many cases of RegisterClass parameters are now RegisterOperand. Contributer: Vladimir Medic git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172284 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove # from the beginning and end of def names. The # is a paste operator ↵Craig Topper2013-01-07
| | | | | | and should only be used with something to paste on either side. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171697 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips] 80 columns.Akira Hatanaka2013-01-04
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171515 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips] Reorder template parameters. Remove class shift_rotate_imm32 andAkira Hatanaka2013-01-04
| | | | | | | | shift_rotate_imm64. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171513 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips] Refactor instructions which move data from or to coprocessors.Akira Hatanaka2013-01-04
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171510 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips] Refactor subword-swap, EXT/INS, load-effective-address and read-hardwareAkira Hatanaka2012-12-21
| | | | | | | | instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170956 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips] Refactor SYNC and multiply/divide instructions.Akira Hatanaka2012-12-21
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170955 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips] Refactor jump, jump register, jump-and-link and nop instructions.Akira Hatanaka2012-12-21
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170952 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips] Refactor load/store left/right and load-link and store-conditionalAkira Hatanaka2012-12-21
| | | | | | | | instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170950 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips] Refactor load/store instructions.Akira Hatanaka2012-12-21
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170948 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips] Refactor LUI instruction.Akira Hatanaka2012-12-21
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170944 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips] Refactor count leading zero or one instructions.Akira Hatanaka2012-12-21
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170942 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips] Refactor sign-extension-in-register instructions.Akira Hatanaka2012-12-21
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170940 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips] Refactor instructions which copy from and to HI/LO registers.Akira Hatanaka2012-12-21
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170939 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips] Refactor logical NOR instructions.Akira Hatanaka2012-12-21
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170937 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips] Refactor SLT (set on less than) instructions. Separate encodingAkira Hatanaka2012-12-20
| | | | | | | | information from the rest. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170664 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips] Remove asm string parameter from pseudo instructions. Add InstrItinClass Akira Hatanaka2012-12-20
| | | | | | | parameter. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170661 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips] Refactor conditional branch instructions with one register operand.Akira Hatanaka2012-12-20
| | | | | | | | Separate encoding information from the rest. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170659 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips] Refactor conditional branch instructions with two register operands.Akira Hatanaka2012-12-20
| | | | | | | | Separate encoding information from the rest. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170657 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips] Change the order of template parameters. Move the default parameters toAkira Hatanaka2012-12-20
| | | | | | | | the end. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170651 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips] Refactor shift instructions with register operands. Separate encodingAkira Hatanaka2012-12-20
| | | | | | | | information from the rest. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170650 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips] Refactor shift immediate instructions. Separate encoding informationAkira Hatanaka2012-12-20
| | | | | | | | from the rest. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170649 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips] Refactor arithmetic and logic instructions with immediate operands.Akira Hatanaka2012-12-20
| | | | | | | | Separate encoding information from the rest. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170648 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips] Refactor arithmetic and logic instructions. Separate encodingAkira Hatanaka2012-12-20
| | | | | | | information from the rest. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170647 91177308-0d34-0410-b5e6-96231b3b80d8
generated by cgit v1.2.3 (git 2.25.1) at 2024-05-26 05:13:55 +0000