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path: root/lib/Target/Mips/MipsInstrFPU.td
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* [mips] Add NaCl target and forbid indexed loads and stores for itPetar Jovanovic2014-02-05
| | | | | | | | | | | | This patch adds NaCl target for Mips. It also forbids indexed loads and stores if the target is NaCl. Patch by Sasa Stankovic. Differential Revision: http://llvm-reviews.chandlerc.com/D2690 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200855 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips][sched] Split IIFmoveC1 into II_M[FT]C1, II_M[FT]HC1, II_DM[FT]C1Daniel Sanders2014-01-21
| | | | | | | | No functional change since the InstrItinData's have been duplicated. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199748 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips][sched] Split IIFStore into II_S[WD]C1, and II_S[WDU]XC1Daniel Sanders2014-01-21
| | | | | | | | No functional change since the InstrItinData's have been duplicated. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199747 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips][sched] Split IIFLoad into II_L[WD]C1, and II_L[WDU]XC1Daniel Sanders2014-01-21
| | | | | | | No functional change since the InstrItinData's have been duplicated. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199743 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips][sched] Renamed II_FsqrtSingle and II_FsqrtDouble to II_SQRT_S and ↵Daniel Sanders2014-01-21
| | | | | | | | | | II_SQRT_D respectively No functional change git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199741 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips][sched] Renamed II_FdivSingle and II_FdivDouble to II_DIV_S and ↵Daniel Sanders2014-01-21
| | | | | | | | | | II_DIV_D respectively No functional change git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199738 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips][sched] Split IIFmulDouble into II_MUL_D, II_MADD_D, II_MSUB_D, ↵Daniel Sanders2014-01-21
| | | | | | | | | | II_NMADD_D, and II_NMSUB_S No functional change since the InstrItinData's have been duplicated. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199737 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips][sched] Split IIFmulSingle into II_MUL_S, II_MADD_S, II_MSUB_S, ↵Daniel Sanders2014-01-21
| | | | | | | | | | II_NMADD_S, and II_NMSUB_S No functional change since the InstrItinData's have been duplicated. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199734 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips][sched] Split IIFadd into II_ADD_[DS], II_SUB_[DS]Daniel Sanders2014-01-21
| | | | | | | | No functional change since the InstrItinData's have been duplicated. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199732 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips][sched] Split IIFcmp into II_C_CC_[SD]Daniel Sanders2014-01-21
| | | | | | | | No functional change since the InstrItinData's have been duplicated. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199728 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips][sched] Split IIFmove into II_C[FT]C1, II_MOV[FNTZ]_[SD], II_MOV_[SD]Daniel Sanders2014-01-21
| | | | | | | | No functional change since the InstrItinData's have been duplicated. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199727 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips][sched] Split IIFcvt into II_(ROUND|TRUNC|CEIL|FLOOR|CVT), II_ABS, II_NEGDaniel Sanders2014-01-21
| | | | | | | | No functional change since the InstrItinData's have been duplicated. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199722 91177308-0d34-0410-b5e6-96231b3b80d8
* Support for microMIPS FPU instructions 2.Zoran Jovanovic2013-12-25
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198009 91177308-0d34-0410-b5e6-96231b3b80d8
* Support for microMIPS FPU instructions 1.Zoran Jovanovic2013-12-20
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@197815 91177308-0d34-0410-b5e6-96231b3b80d8
* This patch implements Mips load/store instructions from/to coprocessor 2. ↵Vladimir Medic2013-09-16
| | | | | | Test cases are added. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190780 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips] Enhance command line option "-mno-ldc1-sdc1" to expand base+index doubleAkira Hatanaka2013-09-07
| | | | | | | | | | | precision loads and stores as well as reg+imm double precision loads and stores. Previously, expansion of loads and stores was done after register allocation, but now it takes place during legalization. As a result, users will see double precision stores and loads being emitted to spill and restore 64-bit FP registers. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190235 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips] Use ptr_rc to simplify definitions of base+index load/store instructions.Akira Hatanaka2013-08-28
| | | | | | | | Also, fix predicates. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189432 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips] Add support for mfhc1 and mthc1.Akira Hatanaka2013-08-20
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188848 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips] Remove predicates that were incorrectly or unnecessarily added.Akira Hatanaka2013-08-20
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188845 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips] Define register class FGRH32 for the high half of the 64-bit floatingAkira Hatanaka2013-08-20
| | | | | | | | | | point registers. We will need this register class later when we add definitions for instructions mfhc1 and mthc1. Also, remove sub-register indices sub_fpeven and sub_fpodd and use sub_lo and sub_hi instead. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188842 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips] Resolve register classes dynamically using ptr_rc to reduce the number ofAkira Hatanaka2013-08-20
| | | | | | | | | | load/store instructions defined. Previously, we were defining load/store instructions for each pointer size (32 and 64-bit), but now we need just one definition. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188830 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips] Rename accumulator register classes and FP register operands.Akira Hatanaka2013-08-08
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188020 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips] Rename register classes CPURegs and CPU64Regs.Akira Hatanaka2013-08-06
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187832 91177308-0d34-0410-b5e6-96231b3b80d8
* This patch implements parsing of mips FCC register operands. The example ↵Vladimir Medic2013-07-30
| | | | | | instructions have been added to test files. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187410 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips] Fix FP conditional move instructions to have explicit FP condition codeAkira Hatanaka2013-07-26
| | | | | | | | register operands. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187242 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips] Fix FP branch instructions to have explicit FP condition code registerAkira Hatanaka2013-07-26
| | | | | | | | operands. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187238 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips] Fix floating point branch, comparison, and conditional move instructionsAkira Hatanaka2013-07-26
| | | | | | | | | | | to have register FCC0 (the first floating point condition code register) in their Uses/Defs list. No intended functionality change. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187233 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips] Delete MFC1_FT_CCR, MTC1_FT_CCR and MOVCCRToCCR.Akira Hatanaka2013-07-19
| | | | | | | | No functionality change. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186642 91177308-0d34-0410-b5e6-96231b3b80d8
* This patch represents Mips utilization of r186388 code that alows asm ↵Vladimir Medic2013-07-16
| | | | | | matcher to emit mnemonics contain '.' characters. This makes asm parser code simpler and more efficient. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186397 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips] Add new InstrItinClasses for move from/to coprocessor instructions andAkira Hatanaka2013-07-02
| | | | | | | | | floating point loads and stores. No changes in functionality. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185399 91177308-0d34-0410-b5e6-96231b3b80d8
* This patch introduces RegisterOperand class into Mips FPU instruction ↵Vladimir Medic2013-06-24
| | | | | | definitions and adds dedicated parser methods to MipsAsmParser. It is the first in a series of patches that should fix the problems with parsing Mips FPU instructions and optimize the code in MipsAsmParser. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184716 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips] Improve instruction selection for pattern (store (fp_to_sint $src), ↵Akira Hatanaka2013-05-16
| | | | | | | | | | | | | | | | | | $ptr). Previously, three instructions were needed: trunc.w.s $f0, $f2 mfc1 $4, $f0 sw $4, 0($2) Now we need only two: trunc.w.s $f0, $f2 swc1 $f0, 0($2) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182053 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips] Fix instruction selection pattern for sint_to_fp node to avoid ↵Akira Hatanaka2013-05-16
| | | | | | | | | | | | | | | | | | | | emitting an invalid instruction sequence. Rather than emitting an int-to-FP move instruction and an int-to-FP conversion instruction during instruction selection, we emit a pseudo instruction which gets expanded post-RA. Without this change, register allocation can possibly insert a floating point register move instruction between the two instructions, which is not valid according to the ISA manual. mtc1 $f4, $4 # int-to-fp move instruction. mov.s $f2, $f4 # move contents of $f4 to $f2. cvt.s.w $f0, $f2 # int-to-fp conversion. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182042 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips] Fix indentation.Akira Hatanaka2013-05-16
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182036 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips] Add option -mno-ldc1-sdc1.Akira Hatanaka2013-05-13
| | | | | | | | | This option is used when the user wants to avoid emitting double precision FP loads and stores. Double precision FP loads and stores are expanded to single precision instructions after register allocation. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181718 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips] Define reg+imm load/store pattern templates.Akira Hatanaka2013-03-30
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178407 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips] Split SelectAddr, which was used to match address patterns, into twoAkira Hatanaka2013-02-15
| | | | | | | | | | | | functions. Set AddedComplexity to determine the order in which patterns are matched. This simplifies selection of floating point loads/stores. No functionality change intended. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175300 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips] Set flag neverHasSideEffects flag on some of the floating point ↵Akira Hatanaka2013-01-25
| | | | | | instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173401 91177308-0d34-0410-b5e6-96231b3b80d8
* This patch tackles the problem of parsing Mips Jack Carter2013-01-12
| | | | | | | | | | | | | | | | | | | | register names in the standalone assembler llvm-mc. Registers such as $A1 can represent either a 32 or 64 bit register based on the instruction using it. In addition, based on the abi, $T0 can represent different 32 bit registers. The problem is resolved by the Mips specific AsmParser td definitions changing to work together. Many cases of RegisterClass parameters are now RegisterOperand. Contributer: Vladimir Medic git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172284 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips] Remove asm string parameter from pseudo instructions. Add InstrItinClass Akira Hatanaka2012-12-20
| | | | | | | parameter. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170661 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips] Delete all floating point instruction classes that are no longer used.Akira Hatanaka2012-12-13
| | | | | | | No functionality change. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170084 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips] Modify definitions of floating point comparison instructions.Akira Hatanaka2012-12-13
| | | | | | | No functionality change. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170077 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips] Modify definitions of floating point branch instructions.Akira Hatanaka2012-12-13
| | | | | | | No functionality change. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170076 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips] Modify definitions of floating point indexed load and store instructions.Akira Hatanaka2012-12-13
| | | | | | | No functionality change. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170075 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips] Modify definitions of floating point multiply-add/sub instructions.Akira Hatanaka2012-12-13
| | | | | | | No functionality change. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170073 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips] Modify definitions of floating point load and store instructions.Akira Hatanaka2012-12-13
| | | | | | | No functionality change. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170072 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips] Modify definitions of move from/to coprocessor instructions.Akira Hatanaka2012-12-13
| | | | | | | No functionality change. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170071 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips] Modify definitions of two register operand floating point instructions.Akira Hatanaka2012-12-13
| | | | | | | No functionality change. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170069 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips] Modify definitions of three register operand floating point instructionsAkira Hatanaka2012-12-13
| | | | | | | | and separate encoding information from the rest. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170066 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips] Move classes that do not belong in MipsInstrFormats.td intoAkira Hatanaka2012-12-13
| | | | | | | | MipsInstrFPU.td. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170061 91177308-0d34-0410-b5e6-96231b3b80d8
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