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path: root/lib/Target/Mips/MipsInstrFormats.td
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* Use branches instead of jumps + variable cleanup. Testcase coming next. ↵Bruno Cardoso Lopes2011-12-06
| | | | | | Patch by Jack Carter git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145912 91177308-0d34-0410-b5e6-96231b3b80d8
* Final patch that completes old JIT support for Mips:Bruno Cardoso Lopes2011-10-18
| | | | | | | | | | | | | | | | -Fix binary codes and rename operands in .td files so that automatically generated function MipsCodeEmitter::getBinaryCodeForInstr gives correct encoding for instructions. -Define new class FMem for instructions that access memory. -Define new class FFRGPR for instructions that move data between GPR and FPU general and control registers. -Define custom encoder methods for memory operands, and also for size operands of ext and ins instructions. -Only static relocation model is currently implemented. Patch by Sasa Stankovic git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142378 91177308-0d34-0410-b5e6-96231b3b80d8
* Move class and instruction definitions for conditional moves to a seperate file.Akira Hatanaka2011-10-17
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142220 91177308-0d34-0410-b5e6-96231b3b80d8
* Add support for conditional branch instructions with 64-bit register operands.Akira Hatanaka2011-10-11
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141694 91177308-0d34-0410-b5e6-96231b3b80d8
* Define classes and multiclasses for FP binary instructions.Akira Hatanaka2011-10-08
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141475 91177308-0d34-0410-b5e6-96231b3b80d8
* Define classes for FP unary instructions and multiclasses for FP-to-fixed pointAkira Hatanaka2011-10-08
| | | | | | | conversion instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141473 91177308-0d34-0410-b5e6-96231b3b80d8
* Mark MipsPseudo isPseudo.Akira Hatanaka2011-09-27
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140598 91177308-0d34-0410-b5e6-96231b3b80d8
* Changed definition of EXT and INS per Bruno's comments.Akira Hatanaka2011-08-17
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137892 91177308-0d34-0410-b5e6-96231b3b80d8
* Add support for ext and ins.Akira Hatanaka2011-08-17
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137804 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix td file comments for Mips.Eric Christopher2011-05-09
| | | | | | | Patch by Liu <proljc@gmail.com>! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131086 91177308-0d34-0410-b5e6-96231b3b80d8
* Reverse unnecessary changes made in r129606 and r129608. There is no change ↵Akira Hatanaka2011-04-15
| | | | | | in functionality. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129612 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix lines that have incorrect indentation or exceed 80 columns. There is no ↵Akira Hatanaka2011-04-15
| | | | | | change in functionality. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129606 91177308-0d34-0410-b5e6-96231b3b80d8
* Added support for FP conditional move instructions and fixed bugs in ↵Akira Hatanaka2011-03-31
| | | | | | handling of FP comparisons. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128650 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove (hopefully) all trailing whitespaces from the mips backend. Patch by ↵Bruno Cardoso Lopes2011-03-04
| | | | | | Hatanaka, Akira git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127003 91177308-0d34-0410-b5e6-96231b3b80d8
* fix emacs language spec's, patch by Edmund Grimley-Evans!Chris Lattner2010-08-17
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111241 91177308-0d34-0410-b5e6-96231b3b80d8
* Fixe typos and 80 column size problemsBruno Cardoso Lopes2008-07-09
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@53272 91177308-0d34-0410-b5e6-96231b3b80d8
* Several changes to Mips backend, experimental fp support being the mostBruno Cardoso Lopes2008-07-05
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | important. - Cleanup in the Subtarget info with addition of new features, not all support yet, but they allow the future inclusion of features easier. Among new features, we have : Arch family info (mips1, mips2, ...), ABI info (o32, eabi), 64-bit integer and float registers, allegrex vector FPU (VFPU), single float only support. - TargetMachine now detects allegrex core. - Added allegrex (Mips32r2) sext_inreg instructions. - *Added Float Point Instructions*, handling single float only, and aliased accesses for 32-bit FPUs. - Some cleanup in FP instruction formats and FP register classes. - Calling conventions improved to support mips 32-bit EABI. - Added Asm Printer support for fp cond codes. - Added support for sret copy to a return register. - EABI support added into LowerCALL and FORMAL_ARGS. - MipsFunctionInfo now keeps a virtual register per function to track the sret on function entry until function ret. - MipsInstrInfo FP support into methods (isMoveInstr, isLoadFromStackSlot, ...), FP cond codes mapping and initial FP Branch Analysis. - Two new Mips SDNode to handle fp branch and compare instructions : FPBrcond, FPCmp - MipsTargetLowering : handling different FP classes, Allegrex support, sret return copy, no homing location within EABI, non 32-bit stack objects arguments, and asm constraint for float. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@53146 91177308-0d34-0410-b5e6-96231b3b80d8
* Added FP instruction formats.Bruno Cardoso Lopes2008-06-08
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@52086 91177308-0d34-0410-b5e6-96231b3b80d8
* Added custom SELECT_CC loweringBruno Cardoso Lopes2008-06-06
| | | | | | | Added special isel for ADDE,SUBE and new patterns to match SUBC,ADDC git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@52031 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove attribution from file headers, per discussion on llvmdev.Chris Lattner2007-12-29
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45418 91177308-0d34-0410-b5e6-96231b3b80d8
* Position Independent Code (PIC) support [1]Bruno Cardoso Lopes2007-10-09
| | | | | | | | - Modified instruction format to handle pseudo instructions - Added LoadAddr SDNode to load symbols. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@42778 91177308-0d34-0410-b5e6-96231b3b80d8
* Instruction Itinerary attribution fixedBruno Cardoso Lopes2007-08-21
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@41224 91177308-0d34-0410-b5e6-96231b3b80d8
* Added InstrItinClass support for instruction formatsBruno Cardoso Lopes2007-08-18
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@41156 91177308-0d34-0410-b5e6-96231b3b80d8
* Change instruction description to split OperandList into OutOperandList andEvan Cheng2007-07-19
| | | | | | | | | | | | | | | | InOperandList. This gives one piece of important information: # of results produced by an instruction. An example of the change: def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2), "add{l} {$src2, $dst|$dst, $src2}", [(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>; => def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2), "add{l} {$src2, $dst|$dst, $src2}", [(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>; git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40033 91177308-0d34-0410-b5e6-96231b3b80d8
* Initial Mips support, here we go! =)Bruno Cardoso Lopes2007-06-06
- Modifications from the last patch included (issues pointed by Evan Cheng are now fixed). - Added more MipsI instructions. - Added more patterns to match branch instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37461 91177308-0d34-0410-b5e6-96231b3b80d8
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