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	Commit message (Collapse)	Author	Age
*	R600: Fix inconsistency in rsq instructions.	Matt Arsenault	2014-06-24
\| \| \| \| \| \| \| \| \| \| \| \| \|	R600 was using a clamped version of rsq, but SI was not. Add a new rsq_clamped intrinsic and use them consistently. It's unclear to me from the documentation what behavior the R600 instructions have, so I assume they have the legacy behavior described by the SI documents. For R600, use RECIPSQRT_IEEE for both llvm.AMDGPU.rsq.legacy and llvm.AMDGPU.rsq. R600 also has RECIPSQRT_FF, which I'm not sure how it fits in here. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211637 91177308-0d34-0410-b5e6-96231b3b80d8
*	R600/SI: Add intrinsics for various math instructions.	Matt Arsenault	2014-06-19
\| \| \| \| \| \| \| \|	These will be used for custom lowering and for library implementations of various math functions, so it's useful to expose these as builtins. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211247 91177308-0d34-0410-b5e6-96231b3b80d8
*	R600/SI: Add intrinsics for brev instructions	Matt Arsenault	2014-06-18
\| \| \| \|	git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211187 91177308-0d34-0410-b5e6-96231b3b80d8
*	R600: Remove AMDIL instruction and register definitions	Tom Stellard	2014-06-13
\| \| \| \| \| \|	Most of these are no longer used any more. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210915 91177308-0d34-0410-b5e6-96231b3b80d8
*	R600: Mostly remove remaining AMDIL intrinsics.	Matt Arsenault	2014-06-12
\| \| \| \| \| \| \| \| \|	Delete all unused ones, and add new AMDGPU named intrinsics for the ones that are. Handle the old AMDIL names for comptability (although remove their GCCBuiltin names) and add tests since there weren't any for these before. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210827 91177308-0d34-0410-b5e6-96231b3b80d8
*	R600/SI: Use v_cvt_f32_ubyte* instructions	Matt Arsenault	2014-06-11
\| \| \| \| \| \| \|	This eliminates extra extract instructions when loading an i8 vector to a float vector. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210666 91177308-0d34-0410-b5e6-96231b3b80d8
*	R600: Add intrinsics for mad24	Matt Arsenault	2014-05-22
\| \| \| \|	git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209456 91177308-0d34-0410-b5e6-96231b3b80d8
*	R600: Match 24-bit arithmetic patterns in a Target DAGCombine	Tom Stellard	2014-04-07
\| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \|	Moving these patterns from TableGen files to PerformDAGCombine() should allow us to generate better code by eliminating unnecessary shifts and extensions earlier. This also fixes a bug where the MAD pattern was calling SimplifyDemandedBits with a 24-bit mask on the first operand even when the full pattern wasn't being matched. This occasionally resulted in some instructions being incorrectly deleted from the program. v2: - Fix bug with 64-bit mul git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205731 91177308-0d34-0410-b5e6-96231b3b80d8
*	R600: Add target nodes for BFM and BFI	Matt Arsenault	2014-03-31
\| \| \| \|	git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205235 91177308-0d34-0410-b5e6-96231b3b80d8
*	R600: Match sign_extend_inreg to BFE instructions	Matt Arsenault	2014-03-17
\| \| \| \|	git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204072 91177308-0d34-0410-b5e6-96231b3b80d8
*	R600: Add support for ISD::FROUND	Tom Stellard	2013-11-27
\| \| \| \| \| \|	NOTE: This is a candidate for the 3.4 branch. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195878 91177308-0d34-0410-b5e6-96231b3b80d8
*	R600: Add support for i8 and i16 local memory stores	Tom Stellard	2013-08-26
\| \| \| \|	git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189223 91177308-0d34-0410-b5e6-96231b3b80d8
*	R600: Add support for i16 and i8 global stores	Tom Stellard	2013-08-16
\| \| \| \| \| \|	Tested-by: Aaron Watry <awatry@gmail.com> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188519 91177308-0d34-0410-b5e6-96231b3b80d8
*	Create an FPOW SDNode opcode def in the target independent .td file rather ↵	Owen Anderson	2013-05-22
\| \| \| \| \| \|	than in a specific backend. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182450 91177308-0d34-0410-b5e6-96231b3b80d8
*	R600: Swap the legality of rotl and rotr	Tom Stellard	2013-05-20
\| \| \| \| \| \|	The hardware supports rotr and not rotl. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182285 91177308-0d34-0410-b5e6-96231b3b80d8
*	R600: Support for indirect addressing v4	Tom Stellard	2013-02-06
\| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \|	Only implemented for R600 so far. SI is missing implementations of a few callbacks used by the Indirect Addressing pass and needs code to handle frame indices. At the moment R600 only supports array sizes of 16 dwords or less. Register packing of vector types is currently disabled, which means that a vec4 is stored in T0_X, T1_X, T2_X, T3_X, rather than T0_XYZW. In order to correctly pack registers in all cases, we will need to implement an analysis pass for R600 that determines the correct vector width for each array. v2: - Add support for i8 zext load from stack. - Coding style fixes v3: - Don't reserve registers for indirect addressing when it isn't being used. - Fix bug caused by LLVM limiting the number of SubRegIndex declarations. v4: - Fix 64-bit defines git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174525 91177308-0d34-0410-b5e6-96231b3b80d8
*	Add R600 backend	Tom Stellard	2012-12-11
	A new backend supporting AMD GPUs: Radeon HD2XXX - HD7XXX git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169915 91177308-0d34-0410-b5e6-96231b3b80d8