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	Commit message (Expand)	Author	Age
*	R600: Use SchedModel enum for is{Trans,Vector}Only functions	Vincent Lejeune	2013-09-04
*	R600: Add support for i8 and i16 local memory stores	Tom Stellard	2013-08-26
*	R600: Add IsExport bit to TableGen instruction definitions	Tom Stellard	2013-08-16
*	Revert "R600: Use SchedModel enum for is{Trans,Vector}Only functions"	Tom Stellard	2013-07-31
*	R600: Use SchedModel enum for is{Trans,Vector}Only functions	Vincent Lejeune	2013-07-31
*	R600: Add local memory support via LDS	Tom Stellard	2013-06-28
*	R600: Add ALUInst bit to tablegen definitions v2	Tom Stellard	2013-06-28
*	R600: Use correct encoding for Vertex Fetch instructions on Cayman	Tom Stellard	2013-06-14
*	R600: Factor the instruction encoding out the RAT_WRITE_CACHELESS_eg class	Tom Stellard	2013-06-14
*	R600: Move instruction encoding definitions into a separate .td file	Tom Stellard	2013-06-14