summaryrefslogtreecommitdiff
path: root/lib/Target/R600/SIInstrInfo.cpp
Commit message (Expand)AuthorAge
* R600/SI: Verify restrictions on div_scale operands.Matt Arsenault2014-06-23
* R600/SI: Add intrinsics for brev instructionsMatt Arsenault2014-06-18
* R600/SI: Match cttz_zero_undefMatt Arsenault2014-06-17
* R600/SI: Match ctlz_zero_undefMatt Arsenault2014-06-17
* R600: Move AMDGPUInstrInfo from AMDGPUTargetMachine into AMDGPUSubtargetTom Stellard2014-06-13
* R600/SI: Emit an error when attempting to spill VGPRs v4Tom Stellard2014-06-10
* R600/SI: Fix a crash when spilling SGPRsTom Stellard2014-06-10
* R600/SI: Implement i64 ctpopMatt Arsenault2014-06-10
* R600/SI: Use bcnt instruction for ctpopMatt Arsenault2014-06-10
* R600/SI: Keep 64-bit not on SALUMatt Arsenault2014-06-09
* Fix typosMatt Arsenault2014-06-03
* R600/SI: Fix a bug with handling of INSERT_SUBREG in SIFixSGPRCopiesTom Stellard2014-05-15
* R600/SI: Try to fix BFE operands when moving to VALUMatt Arsenault2014-05-13
* R600/SI: Prettier display of input modifiersVincent Lejeune2014-05-10
* R600/SI: Teach SIInstrInfo::moveToVALU() how to move S_LOAD_*_IMM instructionsTom Stellard2014-05-09
* R600/SI: Only create one instruction when spilling/restoring register v3Tom Stellard2014-05-02
* R600/SI: Teach moveToVALU how to handle some SMRD instructionsTom Stellard2014-04-30
* [C++] Use 'nullptr'. Target edition.Craig Topper2014-04-25
* R600/SI: Try to use scalar BFE.Matt Arsenault2014-04-18
* R600/SI: Match sign_extend_inreg to s_sext_i32_i8 and s_sext_i32_i16Matt Arsenault2014-04-18
* R600/SI: Teach SIInstrInfo::moveToVALU() how to handle PHI instructionsTom Stellard2014-04-17
* R600/SI: Legalize operands after changing dst reg in FixSGPRCopiesTom Stellard2014-04-17
* R600/SI: Refactor SOPC classes slightly.Matt Arsenault2014-04-11
* R600/SI: Match not instruction.Matt Arsenault2014-04-09
* R600/SI: Handle INSERT_SUBREG in SIFixSGPRCopiesTom Stellard2014-04-07
* R600/SI: Implement shouldConvertConstantLoadToIntImmMatt Arsenault2014-03-31
* R600/SI: Implement SIInstrInfo::isTriviallyRematerializable()Tom Stellard2014-03-31
* R600/SI: Fix extra mov from legalizing 64-bit SALU ops.Matt Arsenault2014-03-24
* R600/SI: Sub-optimial fix for 64-bit immediates with SALU ops.Matt Arsenault2014-03-24
* R600/SI: Fix 64-bit bit ops that require the VALU.Matt Arsenault2014-03-24
* R600/SI: Move splitting 64-bit immediates to separate function.Matt Arsenault2014-03-24
* R600/SI: Fix warning with gcc 4.8.2Tom Stellard2014-03-24
* R600/SI: Move instruction patterns to scalar versions.Matt Arsenault2014-03-21
* R600/SI: Handle MUBUF instructions in SIInstrInfo::moveToVALU()Tom Stellard2014-03-21
* R600/SI: Handle S_MOV_B64 in SIInstrInfo::moveToVALU()Tom Stellard2014-03-21
* R600/SI: Fix implementation of isInlineConstant() used by the verifierTom Stellard2014-03-17
* R600/SI: Add generic checks to SIInstrInfo::verifyInstruction()Tom Stellard2014-03-17
* Phase 2 of the great MachineRegisterInfo cleanup. This time, we're changingOwen Anderson2014-03-13
* Move trivial getter into header.Matt Arsenault2014-03-11
* R600/SI: Initialize M0 and emit S_WQM_B64 whenever DS instructions are usedTom Stellard2014-02-10
* Allow MachineCSE to coalesce trivial subregister copies the same way that it ...Andrew Trick2013-12-17
* R600/SI: Implement spilling of SGPRs v5Tom Stellard2013-11-27
* R600/SI: Fix moveToVALU when the first operand is VSrc.Matt Arsenault2013-11-18
* R600/SI: Fix multiple SGPR reads when using VCC.Matt Arsenault2013-11-18
* R600/SI: Move patterns to match add / sub to scalar instructionsMatt Arsenault2013-11-18
* R600/SI: Fix extra defs of VCC / SCC.Matt Arsenault2013-11-18
* Make method staticMatt Arsenault2013-11-15
* Indentation fixesMatt Arsenault2013-11-14
* Add a commentMatt Arsenault2013-11-14
* R600: Fix uninitialized variable usageTom Stellard2013-11-13
generated by cgit v1.2.3 (git 2.25.1) at 2024-05-04 06:26:44 +0000