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* R600: Move trivial getters into header, use initializer listMatt Arsenault2014-06-27
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211917 91177308-0d34-0410-b5e6-96231b3b80d8
* R600: Don't crash on unhandled instruction in promote allocaMatt Arsenault2014-06-27
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211906 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix missing newline and simplify debug printing.Matt Arsenault2014-06-27
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211850 91177308-0d34-0410-b5e6-96231b3b80d8
* R600: Move load/store ReplaceNodeResults to common code.Matt Arsenault2014-06-27
| | | | | | Future patches will want to custom lower loads on SI. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211848 91177308-0d34-0410-b5e6-96231b3b80d8
* R600/SI: Add FP mode bits to binary.Matt Arsenault2014-06-26
| | | | | | | | The default rounding mode to initialize the mode register needs to be reported to the runtime. Fill in other bits a kernel may be interested in setting for future use. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211791 91177308-0d34-0410-b5e6-96231b3b80d8
* Silencing a warning about isZExtFree hiding an inherited virtual function. ↵Aaron Ballman2014-06-26
| | | | | | No functional change intended. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211783 91177308-0d34-0410-b5e6-96231b3b80d8
* R600: Fix vector FMAMatt Arsenault2014-06-26
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211757 91177308-0d34-0410-b5e6-96231b3b80d8
* R600/SI: Use a ComplexPattern for MUBUF storesTom Stellard2014-06-24
| | | | | | | | Now that non-leaf ComplexPatterns are allowed we can fold all the MUBUF store patterns into the instruction definition. We will also be able to reuse this new ComplexPattern for MUBUF loads and atomic operations. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211644 91177308-0d34-0410-b5e6-96231b3b80d8
* R600: Promote i64 stores to v2i32Tom Stellard2014-06-24
| | | | | | Now we need only one 64-bit pattern for stores. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211643 91177308-0d34-0410-b5e6-96231b3b80d8
* R600: Fix inconsistency in rsq instructions.Matt Arsenault2014-06-24
| | | | | | | | | | | | | R600 was using a clamped version of rsq, but SI was not. Add a new rsq_clamped intrinsic and use them consistently. It's unclear to me from the documentation what behavior the R600 instructions have, so I assume they have the legacy behavior described by the SI documents. For R600, use RECIPSQRT_IEEE for both llvm.AMDGPU.rsq.legacy and llvm.AMDGPU.rsq. R600 also has RECIPSQRT_FF, which I'm not sure how it fits in here. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211637 91177308-0d34-0410-b5e6-96231b3b80d8
* R600: Remove DIV_INFMatt Arsenault2014-06-24
| | | | | | | This corresponded to an amdil instruction which there is a 2 instruction equivalent for. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211616 91177308-0d34-0410-b5e6-96231b3b80d8
* R600/SI: Move pattern to instruction definitionMatt Arsenault2014-06-24
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211614 91177308-0d34-0410-b5e6-96231b3b80d8
* R600/SI: Verify restrictions on div_scale operands.Matt Arsenault2014-06-23
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211524 91177308-0d34-0410-b5e6-96231b3b80d8
* R600/SI: Fix div_scale intrinsic.Matt Arsenault2014-06-23
| | | | | | | The operand that must match one of the others does matter, and implement selecting for it. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211523 91177308-0d34-0410-b5e6-96231b3b80d8
* R600: Remove AMDILISelLoweringMatt Arsenault2014-06-23
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211519 91177308-0d34-0410-b5e6-96231b3b80d8
* R600: Select is not expensive.Matt Arsenault2014-06-23
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211518 91177308-0d34-0410-b5e6-96231b3b80d8
* R600: Move add/sub with overflow out of AMDILISelLoweringMatt Arsenault2014-06-23
| | | | | | Add more tests for these. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211517 91177308-0d34-0410-b5e6-96231b3b80d8
* R600: Move more out of AMDILISelLoweringMatt Arsenault2014-06-23
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211516 91177308-0d34-0410-b5e6-96231b3b80d8
* R600: Don't set fp_round_inreg action.Matt Arsenault2014-06-23
| | | | | | | There's no point in setting this since it seems to only by created in 1 place for ppcf128 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211515 91177308-0d34-0410-b5e6-96231b3b80d8
* R600/SI: Handle i64 sub.Matt Arsenault2014-06-23
| | | | | | We can handle it the same way as add git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211514 91177308-0d34-0410-b5e6-96231b3b80d8
* R600/SI: Move selection of i64 add to separate function.Matt Arsenault2014-06-23
| | | | | | Also don't use a SmallVector for fixed size array. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211513 91177308-0d34-0410-b5e6-96231b3b80d8
* R600: Rename AMDIL fileMatt Arsenault2014-06-23
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211512 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix missing words in sentenceMatt Arsenault2014-06-23
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211511 91177308-0d34-0410-b5e6-96231b3b80d8
* Use helper functionMatt Arsenault2014-06-23
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211510 91177308-0d34-0410-b5e6-96231b3b80d8
* Alphabetize forward declarationsMatt Arsenault2014-06-23
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211509 91177308-0d34-0410-b5e6-96231b3b80d8
* R600: Use LowerSDIVREM for i64 node replaceJan Vesely2014-06-22
| | | | | | | | | v2: move div/rem node replacement to R600ISelLowering make lowerSDIVREM protected Signed-off-by: Jan Vesely <jan.vesely@rutgers.edu> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211478 91177308-0d34-0410-b5e6-96231b3b80d8
* R600: Implement custom SDIVREM.Jan Vesely2014-06-22
| | | | | | | | | | | Instead of separate SDIV/SREM. SDIV used UDIV which in turn used UDIVREM anyway. SREM used SDIV(UDIV->UDIVREM)+MUL+SUB, using UDIVREM directly is more efficient. v2: Don't use all caps names Signed-off-by: Jan Vesely <jan.vesely@rutgers.edu> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211477 91177308-0d34-0410-b5e6-96231b3b80d8
* R600/SI: Add patterns for ctpop inside a branchTom Stellard2014-06-20
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211378 91177308-0d34-0410-b5e6-96231b3b80d8
* R600/SI: Add a pattern for f32 ftruncTom Stellard2014-06-20
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211377 91177308-0d34-0410-b5e6-96231b3b80d8
* R600: Expand vector flog2Tom Stellard2014-06-20
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211376 91177308-0d34-0410-b5e6-96231b3b80d8
* R600: Expand vector fexp2Tom Stellard2014-06-20
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211375 91177308-0d34-0410-b5e6-96231b3b80d8
* R600/SI: SI Control Flow Annotation bug fixedTom Stellard2014-06-20
| | | | | | | | | | | | Mixing of AddAvailableValue and GetValueAtEndOfBlock methods of SSAUpdater leaded to the endless loop generation when the nested loops annotated. This fixes a bug in the OCL_ML/KNN OpenCV test. The test case is too complex for FileCheck and would be very fragile. Patch by: Elena Denisova git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211374 91177308-0d34-0410-b5e6-96231b3b80d8
* R600/SI: Add a VALU pattern for i64 xorTom Stellard2014-06-20
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211373 91177308-0d34-0410-b5e6-96231b3b80d8
* R600: Trivial subtarget feature cleanups.Matt Arsenault2014-06-20
| | | | | | | Remove an unused AMDIL leftover, correct extra periods appearing in the help menu. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211341 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix typosAlp Toker2014-06-19
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211304 91177308-0d34-0410-b5e6-96231b3b80d8
* Convert some assert(0) to llvm_unreachable or fold an 'if' condition into ↵Craig Topper2014-06-19
| | | | | | the assert. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211254 91177308-0d34-0410-b5e6-96231b3b80d8
* R600/SI: Add intrinsics for various math instructions.Matt Arsenault2014-06-19
| | | | | | | | These will be used for custom lowering and for library implementations of various math functions, so it's useful to expose these as builtins. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211247 91177308-0d34-0410-b5e6-96231b3b80d8
* Use stdint macros for specifying size of constantsMatt Arsenault2014-06-18
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211231 91177308-0d34-0410-b5e6-96231b3b80d8
* R600: Handle fnearbyintMatt Arsenault2014-06-18
| | | | | | | | The difference from rint isn't really relevant here, so treat them as equivalent. OpenCL doesn't have nearbyint, so this is sort of pointless other than for completeness. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211229 91177308-0d34-0410-b5e6-96231b3b80d8
* R600/SI: add gather4 and getlod intrinsics (v3)Marek Olsak2014-06-18
| | | | | | | | | | This contains all the previous patches + getlod support on top of it. It doesn't use SDNodes anymore, so it's quite small. It also adds v16i8 to SReg_128, which is used for the sampler descriptor. Reviewed-by: Tom Stellard git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211228 91177308-0d34-0410-b5e6-96231b3b80d8
* Use LL suffix for literal that should be 64-bits.Matt Arsenault2014-06-18
| | | | | | This hopefully fixes Windows git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211225 91177308-0d34-0410-b5e6-96231b3b80d8
* R600: Expand vector fceilJan Vesely2014-06-18
| | | | | | | | | | Move fp64 fceil tests to fceil64.ll v2: rebase Signed-off-by: Jan Vesely <jan.vesely@rutgers.edu> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211194 91177308-0d34-0410-b5e6-96231b3b80d8
* Work around ridiculous warning.Matt Arsenault2014-06-18
| | | | | | Apparently C++ doesn't really have hex floating point constants. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211192 91177308-0d34-0410-b5e6-96231b3b80d8
* R600/SI: Add intrinsics for brev instructionsMatt Arsenault2014-06-18
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211187 91177308-0d34-0410-b5e6-96231b3b80d8
* R600/SI: Prettier operand printing for 64-bit ops.Matt Arsenault2014-06-18
| | | | | | Copy what is done for 32-bit already so the order is about the same. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211186 91177308-0d34-0410-b5e6-96231b3b80d8
* R600: Implement f64 ftrunc, ffloor and fceil.Matt Arsenault2014-06-18
| | | | | | CI has instructions for these, so this fixes them for older hardware. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211183 91177308-0d34-0410-b5e6-96231b3b80d8
* R600: Custom lower f64 frint for pre-CIMatt Arsenault2014-06-18
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211182 91177308-0d34-0410-b5e6-96231b3b80d8
* R600/SI: Temporary fix for f64 fnegMatt Arsenault2014-06-18
| | | | | | | This should be a source modifier, but this unblocks most of my math patches. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211181 91177308-0d34-0410-b5e6-96231b3b80d8
* R600/SI: Comparisons set vcc.Matt Arsenault2014-06-18
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211178 91177308-0d34-0410-b5e6-96231b3b80d8
* R600: Implement 64bit SRAJan Vesely2014-06-18
| | | | | | | | v2: Use capitalized variable name Signed-off-by: Jan Vesely <jan.vesely@rutgers.edu> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211159 91177308-0d34-0410-b5e6-96231b3b80d8
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