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* Fix gcc -Wsign-compare warning in X86DisassemblerTables.cpp.Patrik Hagglund2014-04-28
| | | | | | | | | | X86_MAX_OPERANDS is changed to unsigned. Also, add range-based for loops for affected loops. This in turn needed an ArrayRef instead of a pointer-to-array in InternalInstruction. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207413 91177308-0d34-0410-b5e6-96231b3b80d8
* C++ has a bool type! (And C's had one too, for 15 years...)Richard Smith2014-04-20
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206723 91177308-0d34-0410-b5e6-96231b3b80d8
* More C++ification.Richard Smith2014-04-20
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206722 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove some more C junk from these files.Richard Smith2014-04-20
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206721 91177308-0d34-0410-b5e6-96231b3b80d8
* Don't provide two different definitions of ModRMDecision, OpcodeDecision, ↵Richard Smith2014-04-20
| | | | | | and ContextDecision in different source files (depending on #define magic). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206720 91177308-0d34-0410-b5e6-96231b3b80d8
* Don't define llvm::X86Disassembler::InstructionSpecifier in different ways inRichard Smith2014-04-20
| | | | | | | different source files. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206719 91177308-0d34-0410-b5e6-96231b3b80d8
* What year is it! This file has no reason to be written in C, and has doubly noRichard Smith2014-04-20
| | | | | | | | | | | reason to expose a global symbol 'decodeInstruction' nor to pollute the global scope with a bunch of external linkage entities (some of which conflict with others elsewhere in LLVM). This is just the initial transition to C++; more cleanups to follow. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206717 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix known typosAlp Toker2014-01-24
| | | | | | | Sweep the codebase for common typos. Includes some changes to visible function names that were misspelt. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200018 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove need for MODIFIER_OPCODE in the disassembler tables. AddRegFrms are ↵Craig Topper2014-01-01
| | | | | | really more like OrRegFrm so we don't need a difference since we can just mask bits. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198278 91177308-0d34-0410-b5e6-96231b3b80d8
* AVX-512: decoder for AVX-512, made by Alexey Bader.Elena Demikhovsky2013-12-25
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198013 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove comma from the end of an enum.Craig Topper2013-10-03
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191877 91177308-0d34-0410-b5e6-96231b3b80d8
* Add XOP disassembler support. Fixes PR13933.Craig Topper2013-10-03
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191874 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove unneeded fields from disassembler internal instruction format.Craig Topper2013-10-01
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191731 91177308-0d34-0410-b5e6-96231b3b80d8
* Added encoding prefixes for KNL instructions (EVEX).Elena Demikhovsky2013-07-28
| | | | | | | Added 512-bit operands printing. Added instruction formats for KNL instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187324 91177308-0d34-0410-b5e6-96231b3b80d8
* Update the X86 disassembler to use xacquire and xrelease when appropriate.Kevin Enderby2013-06-20
| | | | | | | | | | | | | | | | | | This is a bit tricky as the xacquire and xrelease hints use the same bytes, 0xf2 and 0xf3, as the repne and rep prefixes. Fortunately llvm has different llvm MCInst Opcode enums for rep/xrelease and repne/xacquire. So to make this work a boolean was added the InternalInstruction struct as part of the Prefix state which is set with the added logic in readPrefixes() when decoding an instruction to determine if these prefix bytes are to be disassembled as xacquire or xrelease. Then we let the matcher pick the normal prefix instructionID and we change the Opcode after that when it is set into the MCInst being created. rdar://11019859 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184490 91177308-0d34-0410-b5e6-96231b3b80d8
* Change unsigned to a uint16_t in static disassembler tables to reduce the ↵Craig Topper2012-09-11
| | | | | | table size. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163594 91177308-0d34-0410-b5e6-96231b3b80d8
* Use const properly so that we dont remove const qualifier from region and MIIRoman Divacky2012-09-05
| | | | | | | by casting. Found with gcc48. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163247 91177308-0d34-0410-b5e6-96231b3b80d8
* Add more indirection to the disassembler tables to reduce amount of space ↵Craig Topper2012-08-01
| | | | | | used to store the operand types and encodings. Store only the unique combinations in a separate table and store indices in the instruction table. Saves about 32K of static data. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161101 91177308-0d34-0410-b5e6-96231b3b80d8
* Tidy up trailing whitespaceCraig Topper2012-07-31
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161027 91177308-0d34-0410-b5e6-96231b3b80d8
* X86: add GATHER intrinsics (AVX2) in LLVMManman Ren2012-06-26
| | | | | | | | | | | | | Support the following intrinsics: llvm.x86.avx2.gather.d.pd, llvm.x86.avx2.gather.q.pd llvm.x86.avx2.gather.d.pd.256, llvm.x86.avx2.gather.q.pd.256 llvm.x86.avx2.gather.d.ps, llvm.x86.avx2.gather.q.ps llvm.x86.avx2.gather.d.ps.256, llvm.x86.avx2.gather.q.ps.256 Modified Disassembler to handle VSIB addressing mode. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159221 91177308-0d34-0410-b5e6-96231b3b80d8
* Updated the llvm-mc disassembler C API to support for the X86 target.Kevin Enderby2012-02-23
| | | | | | | | | | | | | | | | | | | | | | rdar://10873652 As part of this I updated the llvm-mc disassembler C API to always call the SymbolLookUp call back even if there is no getOpInfo call back. If there is a getOpInfo call back that is tried first and then if that gets no information then the SymbolLookUp is called. I also made the code more robust by memset(3)'ing to zero the LLVMOpInfo1 struct before then setting SymbolicOp.Value before for the call to getOpInfo. And also don't use any values from the LLVMOpInfo1 struct if getOpInfo returns 0. And also don't use any of the ReferenceType or ReferenceName values from SymbolLookUp if it returns NULL. rdar://10873563 and rdar://10873683 For the X86 target also fixed bugs so the annotations get printed. Also fixed a few places in the ARM target that was not producing symbolic operands for some instructions. rdar://10878166 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151267 91177308-0d34-0410-b5e6-96231b3b80d8
* Emacs-tag and some comment fix for all ARM, CellSPU, Hexagon, MBlaze, ↵Jia Liu2012-02-18
| | | | | | MSP430, PPC, PTX, Sparc, X86, XCore. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150878 91177308-0d34-0410-b5e6-96231b3b80d8
* Don't mix declarations and code.Benjamin Kramer2012-02-11
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150305 91177308-0d34-0410-b5e6-96231b3b80d8
* Reuse the enum names from X86Desc in the X86Disassembler.Benjamin Kramer2012-02-11
| | | | | | | This requires some gymnastics to make it available for C code. Remove the names from the disassembler tables, making them relocation free. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150303 91177308-0d34-0410-b5e6-96231b3b80d8
* Flatten some of the arrays in the X86 disassembler tables to reduce space ↵Craig Topper2012-02-09
| | | | | | needed to store pointers on 64-bit hosts and reduce relocations needed at startup. Part of PR11953. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150161 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix a ton of comment typos found by codespell. Patch byChris Lattner2011-04-15
| | | | | | | | Luis Felipe Strano Moraes! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129558 91177308-0d34-0410-b5e6-96231b3b80d8
* X86 table-generator and disassembler support for the AVXSean Callanan2011-03-15
| | | | | | | | | | instruction set. This code adds support for the VEX prefix and for the YMM registers accessible on AVX-enabled architectures. Instruction table support that enables AVX instructions for the disassembler is in an upcoming patch. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127644 91177308-0d34-0410-b5e6-96231b3b80d8
* Fixed a bug in the X86 disassembler where a member of theSean Callanan2011-02-21
| | | | | | | | | X86 instruction decode structure was being interpreted as being in units of bits, although it is actually stored in units of bytes. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126147 91177308-0d34-0410-b5e6-96231b3b80d8
* Make the disassembler tables const so they end up in read-only memory.Benjamin Kramer2010-10-23
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117206 91177308-0d34-0410-b5e6-96231b3b80d8
* Eliminated the classification of control registers into %ecr_Sean Callanan2010-05-06
| | | | | | | | | | and %rcr_, leaving just %cr_ which is what people expect. Updated the disassembler to support this unified register set. Added a testcase to verify that the registers continue to be decoded correctly. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103196 91177308-0d34-0410-b5e6-96231b3b80d8
* Fixes to the X86 disassembler. The disassembler will nowSean Callanan2010-04-02
| | | | | | | | return an error status in all failure cases, printing messages to debugs() only when debugging is enabled. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100229 91177308-0d34-0410-b5e6-96231b3b80d8
* More fixes for Visual C++. Replaced several very smallSean Callanan2009-12-23
| | | | | | | static inline functions with macros. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91973 91177308-0d34-0410-b5e6-96231b3b80d8
* Changed REG_* to MODRM_REG_* to avoid conflictsSean Callanan2009-12-22
| | | | | | | with symbols in AuroraUX's global namespace. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91879 91177308-0d34-0410-b5e6-96231b3b80d8
* Table-driven disassembler for the X86 architecture (16-, 32-, and 64-bit Sean Callanan2009-12-19
incarnations), integrated into the MC framework. The disassembler is table-driven, using a custom TableGen backend to generate hierarchical tables optimized for fast decode. The disassembler consumes MemoryObjects and produces arrays of MCInsts, adhering to the abstract base class MCDisassembler (llvm/MC/MCDisassembler.h). The disassembler is documented in detail in - lib/Target/X86/Disassembler/X86Disassembler.cpp (disassembler runtime) - utils/TableGen/DisassemblerEmitter.cpp (table emitter) You can test the disassembler by running llvm-mc -disassemble for i386 or x86_64 targets. Please let me know if you encounter any problems with it. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91749 91177308-0d34-0410-b5e6-96231b3b80d8
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