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path: root/lib/Target/X86/MCTargetDesc/X86BaseInfo.h
Commit message (Expand)AuthorAge
* Re-sort all of the includes with ./utils/sort_includes.py so thatChandler Carruth2014-01-07
* Remove SegOvrBits from X86 TSFlags since they weren't being used.Craig Topper2014-01-06
* Add OpSize16 bit, for instructions which need 0x66 prefix in 16-bit modeCraig Topper2014-01-06
* Remove MRMInitReg form now that it's last use is gone.Craig Topper2013-12-31
* Adding intrinsics to the llvm backend for TBM instruction set.Yunzhong Gao2013-09-27
* Added encoding prefixes for KNL instructions (EVEX).Elena Demikhovsky2013-07-28
* Add CLAC/STAC instruction encoding/decoding supportMichael Liao2013-04-11
* In the X86 back end, getMemoryOperandNo() returns the offsetPreston Gurd2013-04-10
* x86 -- add the XTEST instructionDave Zarzycki2013-03-25
* Fix typo in X86BaseInfo.h that I introduced in r157818.Hans Wennborg2013-01-29
* Add support of RTM from TSX extensionMichael Liao2012-11-08
* Remove 'static' from inline functions defined in header files.Chandler Carruth2012-06-20
* Better comments for TLS-related X86 MachineOperand flags.Hans Wennborg2012-06-04
* Implement the local-dynamic TLS model for x86 (PR3985)Hans Wennborg2012-06-01
* Implement initial-exec TLS model for 32-bit PIC x86Hans Wennborg2012-05-11
* Copied all the VEX prefix encoding code from X86MCCodeEmitter to the x86 JIT ...Pete Cooper2012-04-30
* Add vmfunc instruction to X86 assembler and disassembler.Craig Topper2012-02-19
* Add X86 assembler and disassembler support for AMD SVM instructions. Original...Craig Topper2012-02-18
* Add support for implicit TLS model used with MS VC runtime.Anton Korobeynikov2012-02-11
* Convert assert(0) to llvm_unreachable in X86 Target directory.Craig Topper2012-02-05
* Separate the concept of having memory access in operand 4 from the concept of...Craig Topper2011-12-30
* XOP encoding bits and logic.Jan Sjödin2011-12-12
* This patch contains support for encoding FMA4 instructions andBruno Cardoso Lopes2011-11-25
* Add X86 RORX instructionCraig Topper2011-10-23
* Add X86 PEXTR and PDEP instructions.Craig Topper2011-10-16
* Add X86 BZHI instruction as well as BMI2 feature detection.Craig Topper2011-10-16
* Add X86 BEXTR instruction. This instruction uses VEX.vvvv to encode Operand 3...Craig Topper2011-10-16
* Add support for X86 blsr, blsmsk, and blsi instructions. Required extra work ...Craig Topper2011-10-15
* Add support in the disassembler for ignoring the L-bit on certain VEX instruc...Craig Topper2011-10-04
* Refactor X86 target to separate MC code from Target code.Evan Cheng2011-07-25