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* XOP encoding bits and logic.Jan Sjödin2011-12-12
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146397 91177308-0d34-0410-b5e6-96231b3b80d8
* Handle expressions of the form _GLOBAL_OFFSET_TABLE_-symbol the same way gasRafael Espindola2011-12-10
| | | | | | | | does. The _GLOBAL_OFFSET_TABLE_ is still magical in that we get a R_386_GOTPC, but it doesn't change the immediate in the same way as when the expression has no right hand side symbol. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146311 91177308-0d34-0410-b5e6-96231b3b80d8
* Src2 and src3 were accidentally swapped for the FMA4 rr patterns. Undo this ↵Jan Sjödin2011-12-08
| | | | | | and fix the encoding. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146151 91177308-0d34-0410-b5e6-96231b3b80d8
* This patch contains support for encoding FMA4 instructions andBruno Cardoso Lopes2011-11-25
| | | | | | | | | tablegen patterns for scalar FMA4 operations and intrinsic. Also add tests for vfmaddsd. Patch by Jan Sjodin git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145133 91177308-0d34-0410-b5e6-96231b3b80d8
* Add X86 RORX instructionCraig Topper2011-10-23
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142741 91177308-0d34-0410-b5e6-96231b3b80d8
* Add X86 PEXTR and PDEP instructions.Craig Topper2011-10-16
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142141 91177308-0d34-0410-b5e6-96231b3b80d8
* Add X86 BZHI instruction as well as BMI2 feature detection.Craig Topper2011-10-16
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142122 91177308-0d34-0410-b5e6-96231b3b80d8
* Add X86 BEXTR instruction. This instruction uses VEX.vvvv to encode Operand ↵Craig Topper2011-10-16
| | | | | | 3 instead of Operand 2 so needs special casing in the disassembler and code emitter. Ultimately, should pass this information from tablegen git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142105 91177308-0d34-0410-b5e6-96231b3b80d8
* Add support for X86 blsr, blsmsk, and blsi instructions. Required extra work ↵Craig Topper2011-10-15
| | | | | | because these are the first VEX encoded instructions to use the reg field as an opcode extension. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142082 91177308-0d34-0410-b5e6-96231b3b80d8
* Tidy up a bit more, fix tab and remove trailing whitespacesBruno Cardoso Lopes2011-09-20
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140186 91177308-0d34-0410-b5e6-96231b3b80d8
* Tidy up code!Bruno Cardoso Lopes2011-09-20
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140183 91177308-0d34-0410-b5e6-96231b3b80d8
* Re-write part of VEX encoding logic, to be more easy to read! Also fixBruno Cardoso Lopes2011-08-19
| | | | | | a bug and add a testcase! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138123 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix PR10677. Initial patch and idea by Peter Cooper but I've changed theBruno Cardoso Lopes2011-08-19
| | | | | | implementation! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138029 91177308-0d34-0410-b5e6-96231b3b80d8
* Emit an error is asm parser parsed X86_64 only registers, e.g. %rax, %sil.Evan Cheng2011-07-27
| | | | | | | | | | This can happen in cases where TableGen generated asm matcher cannot check whether a register operand is in the right register class. e.g. mem operands. rdar://8204588 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136292 91177308-0d34-0410-b5e6-96231b3b80d8
* Explicitly cast narrowing conversions inside {}s that will become errors inJeffrey Yasskin2011-07-27
| | | | | | C++0x. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136211 91177308-0d34-0410-b5e6-96231b3b80d8
* More refactoring.Evan Cheng2011-07-25
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135939 91177308-0d34-0410-b5e6-96231b3b80d8
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