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path: root/lib/Target/X86/X86.td
Commit message (Expand)AuthorAge
* X86: Add target description for btver2; make autodetection logic aware of AVX.Benjamin Kramer2013-05-03
* This patch adds the X86FixupLEAs pass, which will reduce instructionPreston Gurd2013-04-25
* [asm parser] Add support for predicating MnemonicAlias based on the assemblerChad Rosier2013-04-18
* Add support of RDSEED defined in AVX2 extensionMichael Liao2013-03-28
* Add the Haswell machine model.Nadav Rotem2013-03-28
* For the current Atom processor, the fastest way to handle a callPreston Gurd2013-03-27
* Add HLE target featureMichael Liao2013-03-26
* Enable SandyBridgeModel for all modern Intel P6 descendants.Jakob Stoklund Olesen2013-03-26
* Add PREFETCHW codegen supportMichael Liao2013-03-26
* added basic support for Intel ADX instructionsKay Tiong Khoo2013-02-14
* Pad Short Functions for Intel AtomPreston Gurd2013-01-08
* Revert revision 171524. Original message:Nadav Rotem2013-01-05
* The current Intel Atom microarchitecture has a feature whereby when a functionPreston Gurd2013-01-04
* Make '-mtune=x86_64' assume fast unaligned memory accesses.Chandler Carruth2012-12-15
* Revert "Make '-mtune=x86_64' assume fast unaligned memory accesses."Chandler Carruth2012-12-10
* Make '-mtune=x86_64' assume fast unaligned memory accesses.Chandler Carruth2012-12-10
* Address a FIXME and update the fast unaligned memory feature for newerChandler Carruth2012-12-10
* Add support of RTM from TSX extensionMichael Liao2012-11-08
* Atom has SIMD instruction set extension up to SSSE3Michael Liao2012-10-25
* Fix 80-column violationCraig Topper2012-10-03
* Add support for AMD Geode.Roman Divacky2012-09-12
* Generic Bypass Slow DivPreston Gurd2012-09-04
* Patch to enable FMA on bdver2 target. Make XOP feature enable FMA4 as well.Anitha Boyapati2012-08-16
* git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162010 91177308-0d34...Anitha Boyapati2012-08-16
* I'm introducing a new machine model to simultaneously allow simpleAndrew Trick2012-07-07
* Rename FMA3 feature flag to just FMA to match gcc so it can be added to clang.Craig Topper2012-06-03
* X86: Rename the CLMUL target feature to PCLMUL.Benjamin Kramer2012-05-31
* Make XOP and FMA4 require SSE4A to match GCC behavior. Use this to simplify B...Craig Topper2012-05-01
* Make XOP imply AVX as its needed to legalize the registers types.Craig Topper2012-05-01
* Make CLMUL and AES imply SSE2 since its needed to legalize the type.Craig Topper2012-05-01
* Enable AVX and FMA4 for AMD Bulldozer processors.Craig Topper2012-05-01
* Enable detection of AVX and AVX2 support through CPUID. Add AVX/AVX2 to corei...Craig Topper2012-04-26
* Emacs-tag and some comment fix for all ARM, CellSPU, Hexagon, MBlaze, MSP430,...Jia Liu2012-02-18
* Use LEA to adjust stack ptr for Atom. Patch by Andy Zhang.Evan Cheng2012-02-07
* Instruction scheduling itinerary for Intel Atom.Andrew Trick2012-02-01
* Rename X86ATTAsmParser -> X86AsmParserDevang Patel2012-01-12
* Add definition for intel asm variant.Devang Patel2012-01-10
* Add definitions for AMD's bobcat (aka btver1)Benjamin Kramer2012-01-10
* Split AsmParser into two components - AsmParser and AsmParserVariantDevang Patel2012-01-09
* Remove AVX hack in X86Subtarget. AVX/AVX2 are now treated as an SSE level. Pr...Craig Topper2012-01-09
* Make FMA4 imply AVX so that YMM registers would be available. Necessitates re...Craig Topper2011-12-30
* Make FMA3 imply AVX needs to be enabled. Particularly because 256-bit types a...Craig Topper2011-12-29
* Add FeaturePOPCNT to all CPU types that lost it was removed from SSE42/SSE4A ...Craig Topper2011-12-29
* Make SSE42 and SSE4A not imply POPCNT. POPCNT should be able to be disabled o...Craig Topper2011-12-29
* Add XOP feature flag.Jan Sjödin2011-12-02
* X86: Turns out bulldozer also supports sse42 and lzcnt.Benjamin Kramer2011-11-30
* X86: Add subtargets for AMD's bulldozer.Benjamin Kramer2011-11-30
* Add intrinsics and feature flag for read/write FS/GS base instructions. Also ...Craig Topper2011-10-30
* Remove NaClModeDavid Meyer2011-10-18
* Add X86 BZHI instruction as well as BMI2 feature detection.Craig Topper2011-10-16
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