summaryrefslogtreecommitdiff
path: root/lib/Target/X86/X86ISelLowering.h
Commit message (Collapse)AuthorAge
* [x86] Make the x86 PACKSSWB, PACKSSDW, PACKUSWB, and PACKUSDWChandler Carruth2014-06-20
| | | | | | | | | | | | | | | instructions available as synthetic SDNodes PACKSS and PACKUS that will select to the correct instruction variants based on the return type. This allows us to use these rather important instructions when lowering vector shuffles. Also moves the relevant instruction definitions to be split out from the fully generic multiclasses to allow them to match these new SDNodes in the same way that the UNPCK instructions do. No functionality should actually be changed here. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211332 91177308-0d34-0410-b5e6-96231b3b80d8
* Revert "X86: elide comparisons after cmpxchg instructions."Tim Northover2014-06-10
| | | | | | | This reverts commit r210523. It was committed prematurely without waiting for review. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210524 91177308-0d34-0410-b5e6-96231b3b80d8
* X86: elide comparisons after cmpxchg instructions.Tim Northover2014-06-10
| | | | | | | | | | | | | | | The C++ and C semantics of the compare_and_swap operations actually require us to return a boolean "success" value. In LLVM terms this means a second comparison of the output of "cmpxchg" against the input desired value. However, x86's "cmpxchg" instruction sets all flags for the comparison formed, so we can skip any secondary comparison. (N.b. this isn't true for cmpxchg8b/16b, which only set ZF). rdar://problem/13201607 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210523 91177308-0d34-0410-b5e6-96231b3b80d8
* Move all of the x86 subtarget initialized variables down into the x86 subtargetEric Christopher2014-06-09
| | | | | | from the x86 target machine. Should be no functional change. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210479 91177308-0d34-0410-b5e6-96231b3b80d8
* Implemented LowerVSELECT to custom lower some instructions.Filipe Cabecinhas2014-05-16
| | | | | | | | No functionality change intended. The types that previously were set to lower as Expand or Legal are doing the same thing with this lowering function. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209042 91177308-0d34-0410-b5e6-96231b3b80d8
* Rename ComputeMaskedBits to computeKnownBits. "Masked" has beenJay Foad2014-05-14
| | | | | | inappropriate since it lost its Mask parameter in r154011. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208811 91177308-0d34-0410-b5e6-96231b3b80d8
* Pass the value type to TLI::getRegisterByNameHal Finkel2014-05-11
| | | | | | | | | | | | | We must validate the value type in TLI::getRegisterByName, because if we don't and the wrong type was used with the IR intrinsic, then we'll assert (because we won't be able to find a valid register class with which to construct the requested copy operation). For PPC64, additionally, the type information is necessary to decide between the 64-bit register and the 32-bit subregister. No functionality change. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208508 91177308-0d34-0410-b5e6-96231b3b80d8
* Add 'override' to getRegisterByName in *ISelLowering.hHal Finkel2014-05-11
| | | | | | No functionality change intended. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208507 91177308-0d34-0410-b5e6-96231b3b80d8
* Implememting named register intrinsicsRenato Golin2014-05-06
| | | | | | | | | | | This patch implements the infrastructure to use named register constructs in programs that need access to specific registers (bare metal, kernels, etc). So far, only the stack pointer is supported as a technology preview, but as it is, the intrinsic can already support all non-allocatable registers from any architecture. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208104 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix i128 div/mod on mingw64Reid Kleckner2014-05-06
| | | | | | | | | | The Win64 docs are very clear that anything larger than 8 bytes is passed by reference, and GCC MinGW64 honors that for __modti3 and friends. Patch by Jameson Nash! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208029 91177308-0d34-0410-b5e6-96231b3b80d8
* [C++11] Add 'override' keywords and remove 'virtual'. Additionally add ↵Craig Topper2014-04-29
| | | | | | 'final' and leave 'virtual' on some methods that are marked virtual without overriding anything and have no obvious overrides themselves. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207511 91177308-0d34-0410-b5e6-96231b3b80d8
* [C++] Use 'nullptr'.Craig Topper2014-04-28
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207394 91177308-0d34-0410-b5e6-96231b3b80d8
* X86: Lower SMUL_LOHI of v4i32 to pmuldq when SSE4.1 is available.Benjamin Kramer2014-04-26
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207318 91177308-0d34-0410-b5e6-96231b3b80d8
* [X86] Implement TargetLowering::getScalingFactorCost hook.Quentin Colombet2014-04-26
| | | | | | | | | | Scaling factors are not free on X86 because every "complex" addressing mode breaks the related instruction into 2 allocations instead of 1. <rdar://problem/16730541> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207301 91177308-0d34-0410-b5e6-96231b3b80d8
* [X86] Add support for Read Time Stamp Counter x86 builtin intrinsics.Andrea Di Biagio2014-04-24
| | | | | | | | | | | | | | | | This patch: - Adds two new X86 builtin intrinsics ('int_x86_rdtsc' and 'int_x86_rdtscp') as GCCBuiltin intrinsics; - Teaches the backend how to lower the two new builtins; - Introduces a common function to lower READCYCLECOUNTER dag nodes and the two new rdtsc/rdtscp intrinsics; - Improves (and extends) the existing x86 test 'rdtsc.ll'; now test 'rdtsc.ll' correctly verifies that both READCYCLECOUNTER and the two new intrinsics work fine for both 64bit and 32bit Subtargets. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207127 91177308-0d34-0410-b5e6-96231b3b80d8
* [X86] Use tablegen instead of DAG combines to match BZHI instructions, asLang Hames2014-04-22
| | | | | | | | | | suggested by Ben Kramer in review of r206738. Thanks again Ben! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206879 91177308-0d34-0410-b5e6-96231b3b80d8
* Change argument order and add explanatory comment to r206130David Blaikie2014-04-14
| | | | | | Changes requested in code review by Eric Christopher of r206130. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206219 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix instruction debug info location during legalizationDavid Blaikie2014-04-13
| | | | | | | | | | | | I found this from a particular GDB test suite case of inlining (something similar is provided as a test case) but came across a few other related cases (other callers of the same functions, and one other instance of the same coding mistake in a separate function). I'm not sure what the best way to test this is (let alone to cover the other cases I discovered), so hopefully this sufficies - open to ideas. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206130 91177308-0d34-0410-b5e6-96231b3b80d8
* AVX-512: insert element to mask vector; store i1 dataElena Demikhovsky2014-04-09
| | | | | | | | Implemented INSERT_VECTOR_ELT operation for v16i1 and v8i1 vectors; Implemented "store" for i1 type git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205850 91177308-0d34-0410-b5e6-96231b3b80d8
* Add DAG parameter to ComputeNumSignBitsForTargetNodeMatt Arsenault2014-04-04
| | | | | | | | This way, you can check the number of sign bits in the operands. The depth parameter it already has is pretty useless without this. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205649 91177308-0d34-0410-b5e6-96231b3b80d8
* Make consistent use of MCPhysReg instead of uint16_t throughout the tree.Craig Topper2014-04-04
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205610 91177308-0d34-0410-b5e6-96231b3b80d8
* isTargetWindows() renamed to isTargetKnownWindowsMSVC()Yaron Keren2014-04-01
| | | | | | | | | | to reflect its current functionality. Based on Takumi NAKAMURA suggestion. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205338 91177308-0d34-0410-b5e6-96231b3b80d8
* Mark a couple of the X86 target classes as final. Allows the compiler to ↵Craig Topper2014-03-31
| | | | | | de-virtualize some internal calls. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205165 91177308-0d34-0410-b5e6-96231b3b80d8
* Add @llvm.clear_cache builtinRenato Golin2014-03-26
| | | | | | | | | | | | | | | | | Implementing the LLVM part of the call to __builtin___clear_cache which translates into an intrinsic @llvm.clear_cache and is lowered by each target, either to a call to __clear_cache or nothing at all incase the caches are unified. Updating LangRef and adding some tests for the implemented architectures. Other archs will have to implement the method in case this builtin has to be compiled for it, since the default behaviour is to bail unimplemented. A Clang patch is required for the builtin to be lowered into the llvm intrinsic. This will be done next. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204802 91177308-0d34-0410-b5e6-96231b3b80d8
* Prune includes in X86 target.Craig Topper2014-03-19
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204216 91177308-0d34-0410-b5e6-96231b3b80d8
* [C++11] Add 'override' keyword to virtual methods that override their base ↵Craig Topper2014-03-09
| | | | | | class. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@203378 91177308-0d34-0410-b5e6-96231b3b80d8
* AVX-512: Fixed extract_vector_elt for v8i1 vectorElena Demikhovsky2014-03-02
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@202624 91177308-0d34-0410-b5e6-96231b3b80d8
* Switch all uses of LLVM_OVERRIDE to just use 'override' directly.Craig Topper2014-03-02
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@202621 91177308-0d34-0410-b5e6-96231b3b80d8
* X86 CodeGenPrep: sink shufflevectors before shiftsTim Northover2014-02-19
| | | | | | | | | | | | | | | | | On x86, shifting a vector by a scalar is significantly cheaper than shifting a vector by another fully general vector. Unfortunately, because SelectionDAG operates on just one basic block at a time, the shufflevector instruction that reveals whether the right-hand side of a shift *is* really a scalar is often not visible to CodeGen when it's needed. This adds another handler to CodeGenPrepare, to sink any useful shufflevector instructions down to the basic block where they're used, predicated on a target hook (since on other architectures, doing so will often just introduce extra real work). rdar://problem/16063505 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@201655 91177308-0d34-0410-b5e6-96231b3b80d8
* AVX-512: Fixed extract_vector_elt for v16i1 and v8i1 vectors.Elena Demikhovsky2014-02-10
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@201066 91177308-0d34-0410-b5e6-96231b3b80d8
* X86: deduplicate V[SZ]EXT_MOVL and V[SZ]EXT nodesTim Northover2014-02-06
| | | | | | | | | | | | | | | | | | | | | | I believe VZEXT_MOVL means "zero all vector elements except the first" (and should have identical input & output types) whereas VZEXT means "zero extend each element of a vector (discarding higher elements if necessary)". For example: (v4i32 (vzext (v16i8 ...))) should zero extend the low 4 bytes of the incoming vector to 32-bits, discarding higher bytes. However, somewhere in the past, these two concepts had become confused, even leading to a nonsensical VSEXT_MOVL. This re-merges the nodes where appropriate (all VSEXT_MOVL -> VSEXT, VZEXT_MOVL -> VZEXT when it's an actual extension). rdar://problem/15981990 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200918 91177308-0d34-0410-b5e6-96231b3b80d8
* Add address space argument to allowsUnalignedMemoryAccess.Matt Arsenault2014-02-05
| | | | | | | On R600, some address spaces have more strict alignment requirements than others. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200887 91177308-0d34-0410-b5e6-96231b3b80d8
* Move matching for x86 BMI BLSI/BLSMSK/BLSR instructions to isel patterns ↵Craig Topper2014-02-05
| | | | | | instead of DAG combine. This weakens the ability to fold loads with them because we aren't able to match patterns that load the same thing twice. But maybe we should fix that if we care. The peephole optimizer will be able to fold some loads in its absense. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200824 91177308-0d34-0410-b5e6-96231b3b80d8
* AVX-512: Added intrinsic for cvtph2ps.Elena Demikhovsky2014-02-05
| | | | | | | | Added VPTESTNM instruction. Added a pattern to vselect (lit tests will follow). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200823 91177308-0d34-0410-b5e6-96231b3b80d8
* [TLI] Add a new hook to TargetLowering to query the target if a load of a ↵Juergen Ributzka2014-01-28
| | | | | | | | | | | | | | | | | constant should be converted to simply the constant itself. Before this patch we used getIntImmCost from TargetTransformInfo to determine if a load of a constant should be converted to just a constant, but the threshold for this was set to an arbitrary value. This value works well for the two targets (X86 and ARM) that implement this target-hook, but it isn't target-independent at all. Now targets have the possibility to decide directly if this optimization should be performed. The default value is set to false to preserve the current behavior. The target hook has been moved to TargetLowering, which removed the last use and need of TargetTransformInfo in SelectionDAG. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200271 91177308-0d34-0410-b5e6-96231b3b80d8
* Replace vfmaddxx213 instructions with their 231-type equivalents in accumulatorLang Hames2014-01-23
| | | | | | | | loops. Writing back to the accumulator (231-type) allows the coalescer to eliminate an extra copy. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199933 91177308-0d34-0410-b5e6-96231b3b80d8
* AVX-512: added VPERM2D VPERM2Q VPERM2PS VPERM2PD instructions,Elena Demikhovsky2014-01-23
| | | | | | | they give better sequences than VPERMI git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199893 91177308-0d34-0410-b5e6-96231b3b80d8
* Make more of the x86 lowering helper functions static.Craig Topper2013-12-29
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198146 91177308-0d34-0410-b5e6-96231b3b80d8
* AVX-512: fixed some patterns for MVT::i1Elena Demikhovsky2013-12-24
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@197981 91177308-0d34-0410-b5e6-96231b3b80d8
* AVX-512: Added implementation of CONCAT_VECTORS for v8i1 vectors (by Alexey ↵Elena Demikhovsky2013-12-17
| | | | | | | | | Bader). Added implementation of "truncate" from integer type (i64/i32/i16/i8) to i1. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@197482 91177308-0d34-0410-b5e6-96231b3b80d8
* AVX-512: Added legal type MVT::i1 and VK1 register for it.Elena Demikhovsky2013-12-16
| | | | | | | | | | Added scalar compare VCMPSS, VCMPSD. Implemented LowerSELECT for scalar FP operations. I replaced FSETCCss, FSETCCsd with one node type FSETCCs. Node extract_vector_elt(v16i1/v8i1, idx) returns an element of type i1. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@197384 91177308-0d34-0410-b5e6-96231b3b80d8
* Refactor a lot of patchpoint/stackmap related code to simplify and make itLang Hames2013-11-29
| | | | | | | | | | | | | | | | | | | | | | | | target independent. Most of the x86 specific stackmap/patchpoint handling was necessitated by the use of the native address-mode format for frame index operands. PEI has now been modified to treat stackmap/patchpoint similarly to DEBUG_INFO, allowing us to use a simple, platform independent register/offset pair for frame indexes on stackmap/patchpoints. Notes: - Folding is now platform independent and automatically supported. - Emiting patchpoints with direct memory references now just involves calling the TargetLoweringBase::emitPatchPoint utility method from the target's XXXTargetLowering::EmitInstrWithCustomInserter method. (See X86TargetLowering for an example). - No more ugly platform-specific operand parsers. This patch shouldn't change the generated output for X86. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195944 91177308-0d34-0410-b5e6-96231b3b80d8
* StackMap: Implement support for DirectMemRefOp.Andrew Trick2013-11-26
| | | | | | | | | | | | | | | | | | | | | | | | | | | | A Direct stack map location records the address of frame index. This address is itself the value that the runtime requested. This differs from IndirectMemRefOp locations, which refer to a stack locations from which the requested values must be loaded. Direct locations can directly communicate the address if an alloca, while IndirectMemRefOp handle register spills. For example: entry: %a = alloca i64... llvm.experimental.stackmap(i32 <ID>, i32 <shadowBytes>, i64* %a) Since both the alloca and stackmap intrinsic are in the entry block, and the intrinsic takes the address of the alloca, the runtime can assume that LLVM will not substitute alloca with any intervening value. This must be verified by the runtime by checking that the stack map's location is a Direct location type. The runtime can then determine the alloca's relative location on the stack immediately after compilation, or at any time thereafter. This differs from Register and Indirect locations, because the runtime can only read the values in those locations when execution reaches the instruction address of the stack map. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195712 91177308-0d34-0410-b5e6-96231b3b80d8
* Add addrspacecast instruction.Matt Arsenault2013-11-15
| | | | | | Patch by Michele Scandale! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194760 91177308-0d34-0410-b5e6-96231b3b80d8
* [Stackmap] Materialize the jump address within the patchpoint noop slide.Juergen Ributzka2013-11-09
| | | | | | | | | | | | | | | This patch moves the jump address materialization inside the noop slide. This enables patching of the materialization itself or its complete removal. This patch also adds the ability to define scratch registers that can be used safely by the code called from the patchpoint intrinsic. At least one scratch register is required, because that one is used for the materialization of the jump address. This patch depends on D2009. Differential Revision: http://llvm-reviews.chandlerc.com/D2074 Reviewed by Andy git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194306 91177308-0d34-0410-b5e6-96231b3b80d8
* AVX-512: implemented extractelement with variable index.Elena Demikhovsky2013-09-12
| | | | | | | Added parsing of mask register and "zeroing" semantic, like {%k1} {z}. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190595 91177308-0d34-0410-b5e6-96231b3b80d8
* Create BEXTR instructions for (and ((sra or srl) x, imm), (2**size - 1)). ↵Craig Topper2013-09-02
| | | | | | Fixes PR17028. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189742 91177308-0d34-0410-b5e6-96231b3b80d8
* Teach X86 backend to create BMI2 BZHI instructions from (and X, (add (shl 1, ↵Craig Topper2013-08-30
| | | | | | Y), -1)). Fixes PR17038. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189653 91177308-0d34-0410-b5e6-96231b3b80d8
* AVX-512: added extend and truncate instructions.Elena Demikhovsky2013-08-29
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189580 91177308-0d34-0410-b5e6-96231b3b80d8
* AVX-512: Added SHIFT instructions.Elena Demikhovsky2013-08-21
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188899 91177308-0d34-0410-b5e6-96231b3b80d8
generated by cgit v1.2.3 (git 2.25.1) at 2024-05-18 20:26:38 +0000