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* Re-apply r211399, "Generate native unwind info on Win64" with a fix to ↵NAKAMURA Takumi2014-06-25
| | | | | | | | | | | | | | | | | | | | | | | ignore SEH pseudo ops in X86 JIT emitter. -- This patch enables LLVM to emit Win64-native unwind info rather than DWARF CFI. It handles all corner cases (I hope), including stack realignment. Because the unwind info is not flexible enough to describe stack frames with a gap of unknown size in the middle, such as the one caused by stack realignment, I modified register spilling code to place all spills into the fixed frame slots, so that they can be accessed relative to the frame pointer. Patch by Vadim Chugunov! Reviewed By: rnk Differential Revision: http://reviews.llvm.org/D4081 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211691 91177308-0d34-0410-b5e6-96231b3b80d8
* Reformat.NAKAMURA Takumi2014-06-25
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211689 91177308-0d34-0410-b5e6-96231b3b80d8
* Revert r211399, "Generate native unwind info on Win64"NAKAMURA Takumi2014-06-22
| | | | | | It broke Legacy JIT Tests on x86_64-{mingw32|msvc}, aka Windows x64. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211480 91177308-0d34-0410-b5e6-96231b3b80d8
* Generate native unwind info on Win64Reid Kleckner2014-06-20
| | | | | | | | | | | | | | | | | | | | This patch enables LLVM to emit Win64-native unwind info rather than DWARF CFI. It handles all corner cases (I hope), including stack realignment. Because the unwind info is not flexible enough to describe stack frames with a gap of unknown size in the middle, such as the one caused by stack realignment, I modified register spilling code to place all spills into the fixed frame slots, so that they can be accessed relative to the frame pointer. Patch by Vadim Chugunov! Reviewed By: rnk Differential Revision: http://reviews.llvm.org/D4081 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211399 91177308-0d34-0410-b5e6-96231b3b80d8
* [X86] Use ADD/SUB instead of INC/DEC for SilvermontAlexey Volkov2014-06-09
| | | | | | | | | | | | | | According to Intel Software Optimization Manual on Silvermont INC or DEC instructions require an additional uop to merge the flags. As a result, a branch instruction depending on an INC or a DEC instruction incurs a 1 cycle penalty. Differential Revision: http://reviews.llvm.org/D3990 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210466 91177308-0d34-0410-b5e6-96231b3b80d8
* Rename ComputeMaskedBits to computeKnownBits. "Masked" has beenJay Foad2014-05-14
| | | | | | inappropriate since it lost its Mask parameter in r154011. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208811 91177308-0d34-0410-b5e6-96231b3b80d8
* [X86] Add peephole for masked rotate amountAdam Nemet2014-03-12
| | | | | | | | | | | | | | | | Extend what's currently done for shift because the HW performs this masking implicitly: (rotl:i32 x, (and y, 31)) -> (rotl:i32 x, y) I use the newly factored out multiclass that was only supporting shifts so far. For testing I extended my testcase for the new rotation idiom. <rdar://problem/15295856> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@203718 91177308-0d34-0410-b5e6-96231b3b80d8
* [X86] Refactor peepholes for masked shift amount into a multiclassAdam Nemet2014-03-12
| | | | | | | | | | | | | | | | | | The peephole (shift x, (and y, 31)) -> (shift x, y) is repeated for each integer type and each shift variant. To improve this a new multiclass is added that covers all integer types. The shift patterns are now instantiated from this. I am planning to add new instances for rotates as well. No functional change intended: * test/CodeGen/X86/shift-and.ll provides coverage * Compared the expanded tablegen output and matched up the defs for these Pat<>s before and after git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@203685 91177308-0d34-0410-b5e6-96231b3b80d8
* X86: Enable ISel of 16-bit MOVBE instructions.Jim Grosbach2014-03-11
| | | | | | | | | | | | | | | | | When the MOVBE instructions are available, use them for 16-bit endian swapping as well as for 32 and 64 bit. The patterns were already present on the instructions, but weren't being matched because the operation was unconditionally marked to 'Expand.' Change that to be conditional on whether the MOVBE instructions are available. Use 'rolw' to implement the in-register version (32 and 64 bit have the dedicated 'bswap' instruction for that). Patch by Louis Gerbarg <lgg@apple.com>. rdar://15479984 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@203524 91177308-0d34-0410-b5e6-96231b3b80d8
* Merge x86 HasOpSizePrefix/HasOpSize16Prefix into a 2-bit OpSize field with 0 ↵Craig Topper2014-02-02
| | | | | | meaning no 0x66 prefix in any mode. Rename Opsize16->OpSize32 and OpSize->OpSize16. The classes now refer to their operand size rather than the mode in which they need a 0x66 prefix. Hopefully can merge REX_W into this as OpSize64. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200626 91177308-0d34-0410-b5e6-96231b3b80d8
* [x86] Remove OpSize16 flag from MOV32r0David Woodhouse2014-01-08
| | | | | | It's not a real instruction any more and doesn't need encoding information. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198778 91177308-0d34-0410-b5e6-96231b3b80d8
* [x86] Add OpSize16 to instructions that need itDavid Woodhouse2014-01-08
| | | | | | | | | This fixes the bulk of 16-bit output, and the corresponding test case x86-16.s now looks mostly like the x86-32.s test case that it was originally based on. A few irrelevant instructions have been dropped, and there are still some corner cases to be fixed in subsequent patches. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198752 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove opcode from MOV32r0 that I accidentally left when I converted it to ↵Craig Topper2014-01-05
| | | | | | Pseudo. Remove FIXME as well. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198564 91177308-0d34-0410-b5e6-96231b3b80d8
* Handle MOV32r0 in expandPostRAPseudo instead of MCInst lowering. No ↵Craig Topper2013-12-31
| | | | | | functional change intended. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198254 91177308-0d34-0410-b5e6-96231b3b80d8
* [x86] Rename In32BitMode predicate to Not64BitModeEric Christopher2013-12-20
| | | | | | | | | | | That's what it actually means, and with 16-bit support it's going to be a little more relevant since in a few corner cases we may actually want to distinguish between 16-bit and 32-bit mode (for example the bare 'push' aliases to pushw/pushl etc.) Patch by David Woodhouse git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@197768 91177308-0d34-0410-b5e6-96231b3b80d8
* Revert "Revert "Mark vastart_save_xmm_regs as changing EFLAGS""Duncan P. N. Exon Smith2013-12-17
| | | | | | | | | | | | | | | | | | | This reverts commit r197481, recommiting r197469 with an extra fix. The vastart_save_xmm_regs pseudo-instruction expands to a test and a branch, so it modifies EFLAGS. Mark it so, or else the scheduler might place it in the middle of another test+branch. This fixes a bug exposed by r192750, which changed the initial scheduler to source-order as part of enabling the MI Scheduler for X86. This re-commit changes the VASTART_SAVE_XMM_REGS custom inserter not to try to save %flags, and adds a test that catches the bad behavior of r197469. <rdar://problem/15627766> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@197503 91177308-0d34-0410-b5e6-96231b3b80d8
* Revert "Mark vastart_save_xmm_regs as changing EFLAGS"Duncan P. N. Exon Smith2013-12-17
| | | | | | | | | This reverts commit r197469. The sanitizer and dragonegg buildbots are failing, I think because of this change. Reverting until I figure out why. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@197481 91177308-0d34-0410-b5e6-96231b3b80d8
* Mark vastart_save_xmm_regs as changing EFLAGSDuncan P. N. Exon Smith2013-12-17
| | | | | | | | | | | | | The vastart_save_xmm_regs pseudo-instruction expands to a test and a branch, so it modifies EFLAGS. Mark it so, or else the scheduler might place it in the middle of another test+branch. This fixes a bug exposed by r192750, which turned on the MI Scheduler for X86. <rdar://problem/15627766> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@197469 91177308-0d34-0410-b5e6-96231b3b80d8
* AVX-512: Implemented CMOV for 512-bit vectorsElena Demikhovsky2013-10-31
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193747 91177308-0d34-0410-b5e6-96231b3b80d8
* Revert part of a fix from 2010, changes since then:Eric Christopher2013-10-14
| | | | | | | | | | | | a) x86-64 TLS has been documented b) the code path should use movq for the correct relocation to be generated. I've also added a fixme for the test case that we should improve the code generated, it should look something like is documented in the tls abi document. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192631 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove some extraneous whitespace.Eric Christopher2013-10-14
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192629 91177308-0d34-0410-b5e6-96231b3b80d8
* Mark that the _ftol2 function used by windows on x86 to handle fptoui ↵Craig Topper2013-07-21
| | | | | | modifies ECX. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186787 91177308-0d34-0410-b5e6-96231b3b80d8
* X86: change MOV64ri64i32 into MOV32ri64Tim Northover2013-06-01
| | | | | | | | | | | | | | The MOV64ri64i32 instruction required hacky MCInst lowering because it was allocated as setting a GR64, but the eventual instruction ("movl") only set a GR32. This converts it into a so-called "MOV32ri64" which still accepts a (appropriate) 64-bit immediate but defines a GR32. This is then converted to the full GR64 by a SUBREG_TO_REG operation, thus keeping everyone happy. This fixes a typo in the opcode field of the original patch, which should make the legact JIT work again (& adds test for that problem). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183068 91177308-0d34-0410-b5e6-96231b3b80d8
* Temporarily Revert "X86: change MOV64ri64i32 into MOV32ri64" as itEric Christopher2013-05-31
| | | | | | seems to have caused PR16192 and other JIT related failures. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183059 91177308-0d34-0410-b5e6-96231b3b80d8
* X86: change MOV64ri64i32 into MOV32ri64Tim Northover2013-05-31
| | | | | | | | | | The MOV64ri64i32 instruction required hacky MCInst lowering because it was allocated as setting a GR64, but the eventual instruction ("movl") only set a GR32. This converts it into a so-called "MOV32ri64" which still accepts a (appropriate) 64-bit immediate but defines a GR32. This is then converted to the full GR64 by a SUBREG_TO_REG operation, thus keeping everyone happy. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182991 91177308-0d34-0410-b5e6-96231b3b80d8
* X86: use sub-register sequences for MOV*r0 operationsTim Northover2013-05-30
| | | | | | | | | | | | Instead of having a bunch of separate MOV8r0, MOV16r0, ... pseudo-instructions, it's better to use a single MOV32r0 (which will expand to "xorl %reg, %reg") and obtain other sizes with EXTRACT_SUBREG and SUBREG_TO_REG. The encoding is smaller and partial register updates can sometimes be avoided. Until recently, this sequence was a barrier to rematerialization though. That should now be fixed so it's an appropriate time to make the change. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182928 91177308-0d34-0410-b5e6-96231b3b80d8
* X86: change zext moves to use sub-register infrastructure.Tim Northover2013-05-30
| | | | | | | | | | | | 32-bit writes on amd64 zero out the high bits of the corresponding 64-bit register. LLVM makes use of this for zero-extension, but until now relied on custom MCLowering and other code to fixup instructions. Now we have proper handling of sub-registers, this can be done by creating SUBREG_TO_REG instructions at selection-time. Should be no change in functionality. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182921 91177308-0d34-0410-b5e6-96231b3b80d8
* Annotate X86InstrCompiler.td with SchedRW lists.Jakob Stoklund Olesen2013-03-25
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177936 91177308-0d34-0410-b5e6-96231b3b80d8
* Annotate X86InstrCompiler.td with SchedRW lists.Jakob Stoklund Olesen2013-03-19
| | | | | | | Add a new WriteZero SchedWrite type for the common dependency-breaking instructions that clear a register. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177442 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove an invalid and unnecessary Pat pattern from the X86 backend:Ulrich Weigand2013-03-19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | def : Pat<(load (i64 (X86Wrapper tglobaltlsaddr :$dst))), (MOV64rm tglobaltlsaddr :$dst)>; This pattern is invalid because the MOV64rm instruction expects a source operand of type "i64mem", which is a subclass of X86MemOperand and thus actually consists of five MI operands, but the Pat provides only a single MI operand ("tglobaltlsaddr" matches an SDnode of type ISD::TargetGlobalTLSAddress and provides a single output). Thus, if the pattern were ever matched, subsequent uses of the MOV64rm instruction pattern would access uninitialized memory. In addition, with the TableGen patch I'm about to check in, this would actually be reported as a build-time error. Fortunately, the pattern does in fact never match, for at least two independent reasons. First, the code generator actually never generates a pattern of the form (load (X86Wrapper (tglobaltlsaddr))). For most combinations of TLS and code models, (tglobaltlsaddr) represents just an offset that needs to be added to some base register, so it is never directly dereferenced. The only exception is the initial-exec model, where (tglobaltlsaddr) refers to the (pc-relative) address of a GOT slot, which *is* in fact directly dereferenced: but in that case, the X86WrapperRIP node is used, not X86Wrapper, so the Pat doesn't match. Second, even if some patterns along those lines *were* ever generated, we should not need an extra Pat pattern to match it. Instead, the original MOV64rm instruction pattern ought to match directly, since it uses an "addr" operand, which is implemented via the SelectAddr C++ routine; this routine is supposed to accept the full range of input DAGs that may be implemented by a single mov instruction, including those cases involving ISD::TargetGlobalTLSAddress (and actually does so e.g. in the initial-exec case as above). To avoid build breaks (due to the above-mentioned error) after the TableGen patch is checked in, I'm removing this Pat here. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177426 91177308-0d34-0410-b5e6-96231b3b80d8
* X86: Disable cmov-memory patterns on subtargets without cmov.Benjamin Kramer2013-02-23
| | | | | | Fixes PR15115. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175962 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix an issue of pseudo atomic instruction DAG scheduleMichael Liao2013-01-22
| | | | | | | | | | | | - Add list of physical registers clobbered in pseudo atomic insts Physical registers are clobbered when pseudo atomic instructions are expanded. Add them in clobber list to prevent DAG scheduler to mis-schedule them after these insns are declared side-effect free. - Add test case from Michael Kuperstein <michael.m.kuperstein@intel.com> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173200 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove # from the beginning and end of def names.Craig Topper2013-01-07
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171696 91177308-0d34-0410-b5e6-96231b3b80d8
* Add hasSideEffects=0 to some atomic instructions.Craig Topper2012-12-26
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171122 91177308-0d34-0410-b5e6-96231b3b80d8
* Add __builtin_setjmp/_longjmp supprt in X86 backendMichael Liao2012-10-15
| | | | | | | | | | | | | - Besides used in SjLj exception handling, __builtin_setjmp/__longjmp is also used as a light-weight replacement of setjmp/longjmp which are used to implementation continuation, user-level threading, and etc. The support added in this patch ONLY addresses this usage and is NOT intended to support SjLj exception handling as zero-cost DWARF exception handling is used by default in X86. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165989 91177308-0d34-0410-b5e6-96231b3b80d8
* X86: fcmov doesn't handle all possible EFLAGS, fall back to a branch for the ↵Benjamin Kramer2012-10-07
| | | | | | | | | others. Otherwise it will try to use SSE patterns and fail horribly if sse is disabled. Fixes PR14035. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165377 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove some encoding bits I forgot to remove from SETB_C16r and SETB_C64r in ↵Craig Topper2012-10-05
| | | | | | r165302. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165303 91177308-0d34-0410-b5e6-96231b3b80d8
* Move expansion of SETB_C(8/16/32/64)r from MCInstLower to ↵Craig Topper2012-10-05
| | | | | | ExpandPostRAPseudos and mark them as pseudos in the td file. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165302 91177308-0d34-0410-b5e6-96231b3b80d8
* Add 'lock' prefix output support in assembly printerMichael Liao2012-09-26
| | | | | | | | | | - Instead of embedding 'lock' into each mnemonic of atomic instructions except 'xchg', we teach X86 assembly printer to output 'lock' prefix similar to or consistent with code emitter. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164659 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix 16-bit atomic inst encoding and keep pseudo-inst starting with '#'Michael Liao2012-09-22
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164453 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix typo in r164357Michael Liao2012-09-22
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164452 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix a typo in r164357Michael Liao2012-09-21
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164372 91177308-0d34-0410-b5e6-96231b3b80d8
* Revise td of X86 atomic instructionsMichael Liao2012-09-21
| | | | | | | | | - Rewirte most atomic instructions in templates for both better maintenance and future extensions, such as HLE in TSX. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164357 91177308-0d34-0410-b5e6-96231b3b80d8
* Re-work X86 code generation of atomic ops with spin-loopMichael Liao2012-09-20
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | - Rewrite/merge pseudo-atomic instruction emitters to address the following issue: * Reduce one unnecessary load in spin-loop previously the spin-loop looks like thisMBB: newMBB: ld t1 = [bitinstr.addr] op t2 = t1, [bitinstr.val] not t3 = t2 (if Invert) mov EAX = t1 lcs dest = [bitinstr.addr], t3 [EAX is implicit] bz newMBB fallthrough -->nextMBB the 'ld' at the beginning of newMBB should be lift out of the loop as lcs (or CMPXCHG on x86) will load the current memory value into EAX. This loop is refined as: thisMBB: EAX = LOAD [MI.addr] mainMBB: t1 = OP [MI.val], EAX LCMPXCHG [MI.addr], t1, [EAX is implicitly used & defined] JNE mainMBB sinkMBB: * Remove immopc as, so far, all pseudo-atomic instructions has all-register form only, there is no immedidate operand. * Remove unnecessary attributes/modifiers in pseudo-atomic instruction td * Fix issues in PR13458 - Add comprehensive tests on atomic ops on various data types. NOTE: Some of them are turned off due to missing functionality. - Revise tests due to the new spin-loop generated. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164281 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix the TCRETURNmi64 bug differently.Jakob Stoklund Olesen2012-09-13
| | | | | | | | | | Add a PatFrag to match X86tcret using 6 fixed registers or less. This avoids folding loads into TCRETURNmi64 using 7 or more volatile registers. <rdar://problem/12282281> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163819 91177308-0d34-0410-b5e6-96231b3b80d8
* Revert r163761 "Don't fold indexed loads into TCRETURNmi64."Jakob Stoklund Olesen2012-09-13
| | | | | | The patch caused "Wrong topological sorting" assertions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163810 91177308-0d34-0410-b5e6-96231b3b80d8
* Don't fold indexed loads into TCRETURNmi64.Jakob Stoklund Olesen2012-09-13
| | | | | | | | | | | | | We don't have enough GR64_TC registers when calling a varargs function with 6 arguments. Since %al holds the number of vector registers used, only %r11 is available as a scratch register. This means that addressing modes using both base and index registers can't be folded into TCRETURNmi64. <rdar://problem/12282281> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163761 91177308-0d34-0410-b5e6-96231b3b80d8
* Implement the local-dynamic TLS model for x86 (PR3985)Hans Wennborg2012-06-01
| | | | | | | | | This implements codegen support for accesses to thread-local variables using the local-dynamic model, and adds a clean-up pass so that the base address for the TLS block can be re-used between local-dynamic access on an execution path. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157818 91177308-0d34-0410-b5e6-96231b3b80d8
* Use ptr_rc_tailcall instead of GR32_TC.Jakob Stoklund Olesen2012-05-09
| | | | | | | | | The getPointerRegClass() hook will return GR32_TC, or whatever is appropriate for the current function. Patch by Yiannis Tsiouris! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156459 91177308-0d34-0410-b5e6-96231b3b80d8
* X86: optimization for -(x != 0)Manman Ren2012-05-07
| | | | | | | | | | | | | | | | | | | This patch will optimize -(x != 0) on X86 FROM cmpl $0x01,%edi sbbl %eax,%eax notl %eax TO negl %edi sbbl %eax %eax In order to generate negl, I added patterns in Target/X86/X86InstrCompiler.td: def : Pat<(X86sub_flag 0, GR32:$src), (NEG32r GR32:$src)>; rdar: 10961709 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156312 91177308-0d34-0410-b5e6-96231b3b80d8
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