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* [x86] Remove some unused instruction format classes.Craig Topper2014-02-26
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@202234 91177308-0d34-0410-b5e6-96231b3b80d8
* [x86] Simplify disassembler code slightly.Craig Topper2014-02-26
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@202233 91177308-0d34-0410-b5e6-96231b3b80d8
* [x86] Switch PAUSE instruction to use XS prefix instead of HasREPPrefix. ↵Craig Topper2014-02-20
| | | | | | Remove HasREPPrefix support from disassembler table generator since its now only used by CodeGenOnly instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@201767 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove special FP opcode maps and instead add enough MRM_XX formats to ↵Craig Topper2014-02-19
| | | | | | handle all the FP operations. This increases format by 1 bit, but decreases opcode map by 1 bit so the TSFlags size doesn't change. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@201649 91177308-0d34-0410-b5e6-96231b3b80d8
* Reduce size of map field in X86 TSFlags since it now requires less bits.Craig Topper2014-02-19
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@201646 91177308-0d34-0410-b5e6-96231b3b80d8
* Put some of the X86 formats in a more logical order.Craig Topper2014-02-19
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@201645 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove A6/A7 opcode maps. They can all be handled with a TB map, opcode of ↵Craig Topper2014-02-19
| | | | | | 0xa6/0xa7, and adding MRM_C0/MRM_E0 forms. Removes 376K from the disassembler tables. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@201641 91177308-0d34-0410-b5e6-96231b3b80d8
* Add PS prefix to some classes I missed in r201538.Craig Topper2014-02-18
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@201551 91177308-0d34-0410-b5e6-96231b3b80d8
* Add an x86 prefix encoding for instructions that would decode to a different ↵Craig Topper2014-02-18
| | | | | | instruction with 0xf2/f3/66 were in front of them, but don't themselves have a prefix. For now this doesn't change any bbehavior, but plan to use it to fix some bugs in the disassembler. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@201538 91177308-0d34-0410-b5e6-96231b3b80d8
* Recommit r201059 and r201060 with hopefully a fix for its original failure.Craig Topper2014-02-10
| | | | | | | | | | | | Original commits messages: Add MRMXr/MRMXm form to X86 for use by instructions which treat the 'reg' field of modrm byte as a don't care value. Will allow for simplification of disassembler code. Simplify a bunch of code by removing the need for the x86 disassembler table builder to know about extended opcodes. The modrm forms are sufficient to convey the information. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@201065 91177308-0d34-0410-b5e6-96231b3b80d8
* Revert r201059 and r201060.Bob Wilson2014-02-10
| | | | | | | | r201059 appears to cause a crash in a bootstrapped build of clang. Craig isn't available to look at it right now, so I'm reverting it while he investigates. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@201064 91177308-0d34-0410-b5e6-96231b3b80d8
* Add MRMXr/MRMXm form to X86 for use by instructions which treat the 'reg' ↵Craig Topper2014-02-10
| | | | | | field of modrm byte as a don't care value. Will allow for simplification of disassembler code. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@201059 91177308-0d34-0410-b5e6-96231b3b80d8
* Merge x86 HasOpSizePrefix/HasOpSize16Prefix into a 2-bit OpSize field with 0 ↵Craig Topper2014-02-02
| | | | | | meaning no 0x66 prefix in any mode. Rename Opsize16->OpSize32 and OpSize->OpSize16. The classes now refer to their operand size rather than the mode in which they need a 0x66 prefix. Hopefully can merge REX_W into this as OpSize64. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200626 91177308-0d34-0410-b5e6-96231b3b80d8
* Merge HasVEXPrefix/HasEVEXPrefix/HasXOPPrefix into a 2-bit 'encoding' field ↵Craig Topper2014-02-02
| | | | | | in TSFlags. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200624 91177308-0d34-0410-b5e6-96231b3b80d8
* Simplify some x86 format classes and remove some ambiguities in their ↵Craig Topper2014-02-01
| | | | | | application. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200608 91177308-0d34-0410-b5e6-96231b3b80d8
* Separate x86 opcode maps and 0x66/0xf2/0xf3 prefixes from each other in the ↵Craig Topper2014-01-31
| | | | | | TSFlags. This greatly simplifies the switch statements in the disassembler tables and the code emitters. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200522 91177308-0d34-0410-b5e6-96231b3b80d8
* Move REP out of the Prefix field of the X86 format. Give it its own bit. It ↵Craig Topper2014-01-31
| | | | | | had special handling anyway and this enables a future patch. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200520 91177308-0d34-0410-b5e6-96231b3b80d8
* [x86] Fix signed relocations for i64i32imm operandsDavid Woodhouse2014-01-30
| | | | | | | | | These should end up (in ELF) as R_X86_64_32S relocs, not R_X86_64_32. Kill the horrid and incomplete special case and FIXME in EncodeInstruction() and set things up so it can infer the signedness from the ImmType just like it can the size and whether it's PC-relative. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200495 91177308-0d34-0410-b5e6-96231b3b80d8
* ]x86] Allow segment and address-size overrides for CMPS[BWLQ] (PR9385)David Woodhouse2014-01-22
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199806 91177308-0d34-0410-b5e6-96231b3b80d8
* [x86] Allow address-size overrides for STOS[BWLQ] (PR9385)David Woodhouse2014-01-22
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199804 91177308-0d34-0410-b5e6-96231b3b80d8
* [x86] Allow segment and address-size overrides for LODS[BWLQ] (PR9385)David Woodhouse2014-01-22
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199803 91177308-0d34-0410-b5e6-96231b3b80d8
* Allow x86 mov instructions to/from memory with absolute address to be ↵Craig Topper2014-01-16
| | | | | | encoded and disassembled with a segment override prefix. Fixes PR16962. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199364 91177308-0d34-0410-b5e6-96231b3b80d8
* AVX-512: optimized scalar compare patternsElena Demikhovsky2014-01-14
| | | | | | | removed AVX512SI format, since it is similar to AVX512BI. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199217 91177308-0d34-0410-b5e6-96231b3b80d8
* Separate the concept of 16-bit/32-bit operand size controlled by 0x66 prefix ↵Craig Topper2014-01-14
| | | | | | | | | | and the current mode from the concept of SSE instructions using 0x66 prefix as part of their encoding without being affected by the mode. This should allow SSE instructions to be encoded correctly in 16-bit mode which r198586 probably broke. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199193 91177308-0d34-0410-b5e6-96231b3b80d8
* [x86] Fix retq/retl handling in 64-bit modeDavid Woodhouse2014-01-13
| | | | | | | | | | | | | | | | | | | | | | | | | This finishes the job started in r198756, and creates separate opcodes for 64-bit vs. 32-bit versions of the rest of the RET instructions too. LRETL/LRETQ are interesting... I can't see any justification for their existence in the SDM. There should be no 'LRETL' in 64-bit mode, and no need for a REX.W prefix for LRETQ. But this is what GAS does, and my Sandybridge CPU and an Opteron 6376 concur when tested as follows: asm __volatile__("pushq $0x1234\nmovq $0x33,%rax\nsalq $32,%rax\norq $1f,%rax\npushq %rax\nlretl $8\n1:"); asm __volatile__("pushq $1234\npushq $0x33\npushq $1f\nlretq $8\n1:"); asm __volatile__("pushq $0x33\npushq $1f\nlretq\n1:"); asm __volatile__("pushq $0x1234\npushq $0x33\npushq $1f\nlretq $8\n1:"); cf. PR8592 and commit r118903, which added LRETQ. I only added LRETIQ to match it. I don't quite understand how the Intel syntax parsing for ret instructions is working, despite r154468 allegedly fixing it. Aren't the explicitly sized 'retw', 'retd' and 'retq' supposed to work? I have at least made the 'lretq' work with (and indeed *require*) the 'q'. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199106 91177308-0d34-0410-b5e6-96231b3b80d8
* AVX-512: Embedded Rounding Control - encoding and printingElena Demikhovsky2014-01-13
| | | | | | | Changed intrinsics for vrcp14/vrcp28 vrsqrt14/vrsqrt28 - aligned with GCC. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199102 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove SegOvrBits from X86 TSFlags since they weren't being used.Craig Topper2014-01-06
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198588 91177308-0d34-0410-b5e6-96231b3b80d8
* Add OpSize16 bit, for instructions which need 0x66 prefix in 16-bit modeCraig Topper2014-01-06
| | | | | | | | | | | | | | | | | | | The 0x66 prefix toggles between 16-bit and 32-bit addressing mode. So in 32-bit mode it is used to switch to 16-bit addressing mode for the following instruction, while in 16-bit mode it's the other way round — it's used to switch to 32-bit mode instead. Thus, emit the 0x66 prefix byte for OpSize only in 32-bit (and 64-bit) mode, and introduce a new OpSize16 bit which is used in 16-bit mode instead. This is just the basic infrastructure for that change; a subsequent patch will add the new OpSize16 bit to the 32-bit instructions that need it. Patch from David Woodhouse. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198586 91177308-0d34-0410-b5e6-96231b3b80d8
* Add a new x86 specific instruction flag to force some isCodeGenOnly ↵Craig Topper2014-01-05
| | | | | | instructions to go through to the disassembler tables without resorting to string matches. Apply flag to all _REV instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198543 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove MRMInitReg form now that it's last use is gone.Craig Topper2013-12-31
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198257 91177308-0d34-0410-b5e6-96231b3b80d8
* [x86] Rename In32BitMode predicate to Not64BitModeEric Christopher2013-12-20
| | | | | | | | | | | That's what it actually means, and with 16-bit support it's going to be a little more relevant since in a few corner cases we may actually want to distinguish between 16-bit and 32-bit mode (for example the bare 'push' aliases to pushw/pushl etc.) Patch by David Woodhouse git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@197768 91177308-0d34-0410-b5e6-96231b3b80d8
* Add in64BitMode/in32BitMode to the MMX/SSE2/AVX maskmovq/dq instructions. ↵Craig Topper2013-10-09
| | | | | | This way the asm parser will pick the right one based on the mode. Instruction selection already did the right thing based on the pointer size. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192266 91177308-0d34-0410-b5e6-96231b3b80d8
* AVX-512: Added TB prefix to all instructions without prefixes,Elena Demikhovsky2013-10-02
| | | | | | | otherwise encoding fails after the last change in X86MCCodeEmitter.cpp. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191812 91177308-0d34-0410-b5e6-96231b3b80d8
* Adding intrinsics to the llvm backend for TBM instruction set.Yunzhong Gao2013-09-27
| | | | | | | | Phabricator code review is located here: http://llvm-reviews.chandlerc.com/D1750 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191539 91177308-0d34-0410-b5e6-96231b3b80d8
* Adds support for Atom Silvermont (SLM) - -march=slmPreston Gurd2013-09-13
| | | | | | | | | | | | | | Implements Instruction scheduler latencies for Silvermont, using latencies from the Intel Silvermont Optimization Guide. Auto detects SLM. Turns on post RA scheduler when generating code for SLM. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190717 91177308-0d34-0410-b5e6-96231b3b80d8
* AVX-512: Added VMOVD, VMOVQ, VMOVSS, VMOVSD instructions.Elena Demikhovsky2013-08-18
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188637 91177308-0d34-0410-b5e6-96231b3b80d8
* Added encoding prefixes for KNL instructions (EVEX).Elena Demikhovsky2013-07-28
| | | | | | | Added 512-bit operands printing. Added instruction formats for KNL instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187324 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix the move to/from accumulator register instructions that use a full 64-bitKevin Enderby2013-07-22
| | | | | | | | | absolute address encoded in the instruction. rdar://8612627 and rdar://14299221 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186878 91177308-0d34-0410-b5e6-96231b3b80d8
* Removed PackedDouble domain from scalar instructions. Added more formats for ↵Elena Demikhovsky2013-06-09
| | | | | | the scalar stuff. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183626 91177308-0d34-0410-b5e6-96231b3b80d8
* removed commented linesElena Demikhovsky2013-05-21
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182377 91177308-0d34-0410-b5e6-96231b3b80d8
* Removed SSEPacked domain from all forms (AVX, SSE, signed, unsigned) scalar ↵Elena Demikhovsky2013-05-21
| | | | | | | | | compare instructions, like COMISS, COMISD. No functional changes. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182371 91177308-0d34-0410-b5e6-96231b3b80d8
* Add CLAC/STAC instruction encoding/decoding supportMichael Liao2013-04-11
| | | | | | | | | As these two instructions in AVX extension are privileged instructions for special purpose, it's only expected to be used in inlined assembly. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179266 91177308-0d34-0410-b5e6-96231b3b80d8
* Add the X86 FMAs to the scheduling model.Nadav Rotem2013-03-28
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178303 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove IIC_DEFAULT from X86Schedule.tdJakob Stoklund Olesen2013-03-25
| | | | | | | | All the instructions tagged with IIC_DEFAULT had nothing in common, and we already have a NoItineraries class to represent untagged instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177937 91177308-0d34-0410-b5e6-96231b3b80d8
* x86 -- add the XTEST instructionDave Zarzycki2013-03-25
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177888 91177308-0d34-0410-b5e6-96231b3b80d8
* X86: Make sure we account for the FMA4 register immediate value, otherwise ↵Benjamin Kramer2013-01-22
| | | | | | | | rip-rel relocations will be off by one byte. PR15040. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173176 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix execution domain for packed FMA4 instructions.Craig Topper2012-11-21
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168417 91177308-0d34-0410-b5e6-96231b3b80d8
* Add support of RTM from TSX extensionMichael Liao2012-11-08
| | | | | | | | | | - Add RTM code generation support throught 3 X86 intrinsics: xbegin()/xend() to start/end a transaction region, and xabort() to abort a tranaction region git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167573 91177308-0d34-0410-b5e6-96231b3b80d8
* Introduce 'UseSSEx' to force SSE legacy encodingMichael Liao2012-08-30
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | - Add 'UseSSEx' to force SSE legacy insn not being selected when AVX is enabled. As the penalty of inter-mixing SSE and AVX instructions, we need prevent SSE legacy insn from being generated except explicitly specified through some intrinsics. For patterns supported by both SSE and AVX, so far, we force AVX insn will be tried first relying on AddedComplexity or position in td file. It's error-prone and introduces bugs accidentally. 'UseSSEx' is disabled when AVX is turned on. For SSE insns inherited by AVX, we need this predicate to force VEX encoding or SSE legacy encoding only. For insns not inherited by AVX, we still use the previous predicates, i.e. 'HasSSEx'. So far, these insns fall into the following categories: * SSE insns with MMX operands * SSE insns with GPR/MEM operands only (xFENCE, PREFETCH, CLFLUSH, CRC, and etc.) * SSE4A insns. * MMX insns. * x87 insns added by SSE. 2 test cases are modified: - test/CodeGen/X86/fast-isel-x86-64.ll AVX code generation is different from SSE one. 'vcvtsi2sdq' cannot be selected by fast-isel due to complicated pattern and fast-isel fallback to materialize it from constant pool. - test/CodeGen/X86/widen_load-1.ll AVX code generation is different from SSE one after fixing SSE/AVX inter-mixing. Exec-domain fixing prefers 'vmovapd' instead of 'vmovaps'. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162919 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix patterns for CVTTPS2DQ to specify SSE2 instead of SSE1.Craig Topper2012-07-30
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160941 91177308-0d34-0410-b5e6-96231b3b80d8
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