| Commit message (Expand) | Author | Age |
|---|
| * | Eliminate or_not_add and just use AddedComplexity so isel tries or_is_add pat... | Evan Cheng | 2010-01-12 |
| * | Reapply the MOV64r0 patch, with a fix: MOV64r0 clobbers EFLAGS. | Dan Gohman | 2010-01-12 |
| * | Extend r93152 to work on OR r, r. If the source set bits are known not to ove... | Evan Cheng | 2010-01-11 |
| * | Revert 93158. It's breaking quite a few x86_64 tests. | Evan Cheng | 2010-01-11 |
| * | Do not turn 8-bit OR to ADD since ADD8ri is not 3-addressfiable. | Evan Cheng | 2010-01-11 |
| * | Re-instate MOV64r0 and MOV16r0, with adjustments to work with the | Dan Gohman | 2010-01-11 |
| * | Pattern top-level operators don't need to be restricted to a | Dan Gohman | 2010-01-11 |
| * | Select an OR with immediate as an ADD if the input bits are known zero. This ... | Evan Cheng | 2010-01-11 |
| * | Fix what looks to me obvious instruction definition bugs. | Evan Cheng | 2010-01-08 |
| * | Remove the SDNPAssociative properties for the flags-producing | Dan Gohman | 2010-01-05 |
| * | Add SDNPCommutative and SDNPAssociative to several X86 target nodes. | Dan Gohman | 2010-01-04 |
| * | PR5886: Make sure IMUL32m is marked as setting EFLAGS, so scheduling doesn't | Eli Friedman | 2009-12-26 |
| * | really remove the instruction, don't just comment it out | Chris Lattner | 2009-12-23 |
| * | completely eliminate the MOV16r0 'instruction'. The only | Chris Lattner | 2009-12-23 |
| * | stop pattern matching 16-bit zero's of a register to MOV16r0, | Chris Lattner | 2009-12-23 |
| * | Remove target attribute break-sse-dep. Instead, do not fold load into sse par... | Evan Cheng | 2009-12-22 |
| * | On recent Intel u-arch's, folding loads into some unary SSE instructions can | Evan Cheng | 2009-12-18 |
| * | Instruction fixes, added instructions, and AsmString changes in the | Sean Callanan | 2009-12-18 |
| * | Re-enable 91381 with fixes. | Evan Cheng | 2009-12-16 |
| * | Use sbb x, x to materialize carry bit in a GPR. The result is all one's or al... | Evan Cheng | 2009-12-15 |
| * | Fix an obvious bug. No test case since LEA16r is not being used. | Evan Cheng | 2009-12-12 |
| * | Minor whitespace fixes. | Dan Gohman | 2009-11-30 |
| * | Remove ISD::DEBUG_LOC and ISD::DBG_LABEL, which are no longer used. | Dan Gohman | 2009-11-23 |
| * | Use a tab in INT3's asm string, for consistency. | Dan Gohman | 2009-11-11 |
| * | Do not infer the target type for COPY_TO_REGCLASS from dest regclass, this wo... | Anton Korobeynikov | 2009-11-02 |
| * | Initial x86 support for BlockAddresses. | Dan Gohman | 2009-10-30 |
| * | Rename usesCustomDAGSchedInserter to usesCustomInserter, and update a | Dan Gohman | 2009-10-29 |
| * | Following r84485, add Defs = [EFLAGS] to the 32-bit lock instructions too. | Dan Gohman | 2009-10-20 |
| * | remove strings from instructions who are never asmprinted. | Chris Lattner | 2009-10-19 |
| * | remove the asmstring, it is now dead. Improve comment. | Chris Lattner | 2009-09-20 |
| * | kill off printPICLabel now, it's specialness is handled by | Chris Lattner | 2009-09-20 |
| * | Add an intel syntax MCInstPrinter implementation. You can now | Chris Lattner | 2009-09-20 |
| * | Add support for using the FLAGS result of or, xor, and and instructions | Dan Gohman | 2009-09-18 |
| * | Added RCL and RCR (rotate left and right with a | Sean Callanan | 2009-09-18 |
| * | Added the LODS (load byte into register, usually | Sean Callanan | 2009-09-16 |
| * | Added the LAR (load segment access rights) | Sean Callanan | 2009-09-16 |
| * | Added the LOOP family of instructions to the Intel | Sean Callanan | 2009-09-16 |
| * | Added an alternate form of register-register CMP | Sean Callanan | 2009-09-16 |
| * | Added the ENTER instruction, which sets up a stack | Sean Callanan | 2009-09-16 |
| * | Added the definitions for one-bit left shifts to | Sean Callanan | 2009-09-16 |
| * | Added far return instructions (that is, returns to | Sean Callanan | 2009-09-15 |
| * | Updated comments per Eli's suggestion. | Sean Callanan | 2009-09-15 |
| * | Added register-to-register ADD instructions to the | Sean Callanan | 2009-09-15 |
| * | Added a new register class for segment registers | Sean Callanan | 2009-09-15 |
| * | Modified the Intel instruction tables to include | Sean Callanan | 2009-09-15 |
| * | Added the WAIT instruction to the Intel tables, | Sean Callanan | 2009-09-12 |
| * | Added CMPS (string comparison) instructions for all | Sean Callanan | 2009-09-12 |
| * | Added SCAS instructions in their 8, 16, 32, and | Sean Callanan | 2009-09-12 |
| * | Added ADC, SUB, SBB, and OR instructions that operate | Sean Callanan | 2009-09-11 |
| * | Added XOR instructions for rAX and immediates of | Sean Callanan | 2009-09-10 |
