llvm - Unofficial llvm GIT mirror used in EmbToolkit

	Commit message (Expand)	Author	Age
*	Merge x86 HasOpSizePrefix/HasOpSize16Prefix into a 2-bit OpSize field with 0 ...	Craig Topper	2014-02-02
*	Separate the concept of 16-bit/32-bit operand size controlled by 0x66 prefix ...	Craig Topper	2014-01-14
*	[x86] Add OpSize16 to instructions that need it	David Woodhouse	2014-01-08
*	Changed register names (and pointer keywords) to be lower case when using Int...	Craig Topper	2013-07-31
*	Fix typo. Change %cl to CL in Intel pattern.	Craig Topper	2013-07-22
*	whitespace	Nadav Rotem	2013-05-04
*	Annotate shifts and rotates with SchedRW lists.	Jakob Stoklund Olesen	2013-03-25
*	Add hasSideEffects=0 to some shift and rotate instructions. None of which are...	Craig Topper	2012-12-27
*	Add SARX/SHRX/SHLX code generation support	Michael Liao	2012-09-26
*	Add RORX code generation support	Michael Liao	2012-09-26
*	Emacs-tag and some comment fix for all ARM, CellSPU, Hexagon, MBlaze, MSP430,...	Jia Liu	2012-02-18
*	Instruction scheduling itinerary for Intel Atom.	Andrew Trick	2012-02-01
*	Intel style asm variant does not need '%' prefix.	Devang Patel	2012-01-03
*	Add X86 SARX, SHRX, and SHLX instructions.	Craig Topper	2011-10-23
*	Add X86 RORX instruction	Craig Topper	2011-10-23
*	rework the rotate-by-1 instructions to be defined like the	Chris Lattner	2010-11-06
*	integrate the 64-bit shifts into X86InstrShiftRotate.td. Enough for tonight.	Chris Lattner	2010-10-05
*	move 32-bit shift and rotates out to their own file.	Chris Lattner	2010-10-05