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path: root/lib/Target/X86/X86InstrShiftRotate.td
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* Merge x86 HasOpSizePrefix/HasOpSize16Prefix into a 2-bit OpSize field with 0 ↵Craig Topper2014-02-02
| | | | | | meaning no 0x66 prefix in any mode. Rename Opsize16->OpSize32 and OpSize->OpSize16. The classes now refer to their operand size rather than the mode in which they need a 0x66 prefix. Hopefully can merge REX_W into this as OpSize64. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200626 91177308-0d34-0410-b5e6-96231b3b80d8
* Separate the concept of 16-bit/32-bit operand size controlled by 0x66 prefix ↵Craig Topper2014-01-14
| | | | | | | | | | and the current mode from the concept of SSE instructions using 0x66 prefix as part of their encoding without being affected by the mode. This should allow SSE instructions to be encoded correctly in 16-bit mode which r198586 probably broke. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199193 91177308-0d34-0410-b5e6-96231b3b80d8
* [x86] Add OpSize16 to instructions that need itDavid Woodhouse2014-01-08
| | | | | | | | | This fixes the bulk of 16-bit output, and the corresponding test case x86-16.s now looks mostly like the x86-32.s test case that it was originally based on. A few irrelevant instructions have been dropped, and there are still some corner cases to be fixed in subsequent patches. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198752 91177308-0d34-0410-b5e6-96231b3b80d8
* Changed register names (and pointer keywords) to be lower case when using ↵Craig Topper2013-07-31
| | | | | | | | | | Intel X86 assembler syntax. Patch by Richard Mitton. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187476 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix typo. Change %cl to CL in Intel pattern.Craig Topper2013-07-22
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186815 91177308-0d34-0410-b5e6-96231b3b80d8
* whitespaceNadav Rotem2013-05-04
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181137 91177308-0d34-0410-b5e6-96231b3b80d8
* Annotate shifts and rotates with SchedRW lists.Jakob Stoklund Olesen2013-03-25
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177935 91177308-0d34-0410-b5e6-96231b3b80d8
* Add hasSideEffects=0 to some shift and rotate instructions. None of which ↵Craig Topper2012-12-27
| | | | | | are currently used by code generation. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171137 91177308-0d34-0410-b5e6-96231b3b80d8
* Add SARX/SHRX/SHLX code generation supportMichael Liao2012-09-26
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164675 91177308-0d34-0410-b5e6-96231b3b80d8
* Add RORX code generation supportMichael Liao2012-09-26
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164674 91177308-0d34-0410-b5e6-96231b3b80d8
* Emacs-tag and some comment fix for all ARM, CellSPU, Hexagon, MBlaze, ↵Jia Liu2012-02-18
| | | | | | MSP430, PPC, PTX, Sparc, X86, XCore. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150878 91177308-0d34-0410-b5e6-96231b3b80d8
* Instruction scheduling itinerary for Intel Atom.Andrew Trick2012-02-01
| | | | | | | | | | | | | | Adds an instruction itinerary to all x86 instructions, giving each a default latency of 1, using the InstrItinClass IIC_DEFAULT. Sets specific latencies for Atom for the instructions in files X86InstrCMovSetCC.td, X86InstrArithmetic.td, X86InstrControl.td, and X86InstrShiftRotate.td. The Atom latencies for the remainder of the x86 instructions will be set in subsequent patches. Adds a test to verify that the scheduler is working. Also changes the scheduling preference to "Hybrid" for i386 Atom, while leaving x86_64 as ILP. Patch by Preston Gurd! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149558 91177308-0d34-0410-b5e6-96231b3b80d8
* Intel style asm variant does not need '%' prefix.Devang Patel2012-01-03
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147453 91177308-0d34-0410-b5e6-96231b3b80d8
* Add X86 SARX, SHRX, and SHLX instructions.Craig Topper2011-10-23
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142779 91177308-0d34-0410-b5e6-96231b3b80d8
* Add X86 RORX instructionCraig Topper2011-10-23
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142741 91177308-0d34-0410-b5e6-96231b3b80d8
* rework the rotate-by-1 instructions to be defined like theChris Lattner2010-11-06
| | | | | | | | | | | | | | shift-by-1 instructions, where the asmstring doesn't contain the implicit 1. It turns out that a bunch of these rotate instructions were completely broken because they used 1 instead of $1. This fixes assembly mismatches on "rclb $1, %bl" and friends, where we used to generate the 3 byte form, we now generate the proper 2-byte form. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118355 91177308-0d34-0410-b5e6-96231b3b80d8
* integrate the 64-bit shifts into X86InstrShiftRotate.td. Enough for tonight.Chris Lattner2010-10-05
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115608 91177308-0d34-0410-b5e6-96231b3b80d8
* move 32-bit shift and rotates out to their own file.Chris Lattner2010-10-05
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115607 91177308-0d34-0410-b5e6-96231b3b80d8
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