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path: root/lib/Target/X86/X86MCInstLower.cpp
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* Make X86::FsFLD0SS / FsFLD0SD real pseudo-instructions.Jakob Stoklund Olesen2011-11-29
| | | | | | | | | Like V_SET0, these instructions are expanded by ExpandPostRA to xorps / vxorps so they can participate in execution domain swizzling. This also makes the AVX variants redundant. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145440 91177308-0d34-0410-b5e6-96231b3b80d8
* Use 256-bit vcmpeqd for creating an all ones vector when AVX2 is enabled.Craig Topper2011-11-19
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145004 91177308-0d34-0410-b5e6-96231b3b80d8
* This commit introduces two fake instructions MORESTACK_RET andRafael Espindola2011-10-26
| | | | | | | | | | | | MORESTACK_RET_RESTORE_R10; which are lowered to a RET and a RET followed by a MOV respectively. Having a fake instruction prevents the verifier from seeing a MachineBasicBlock end with a non-terminator (MOV). It also prevents the rather eccentric case of a MachineBasicBlock ending with RET but having successors nevertheless. Patch by Sanjoy Das. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143062 91177308-0d34-0410-b5e6-96231b3b80d8
* Teach the MC to output code/data region marker labels in MachO and ELF ↵Owen Anderson2011-10-04
| | | | | | modes. These are used by disassemblers to provide better disassembly, particularly on targets like ARM Thumb that like to intermingle data in the TEXT segment. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141135 91177308-0d34-0410-b5e6-96231b3b80d8
* Expand the x86 V_SET0* pseudos right after register allocation.Jakob Stoklund Olesen2011-09-29
| | | | | | | This also makes it possible to reduce the number of pseudo instructions and get rid of the encoding information. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140776 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix atomic load and store on x86 to pass -verify-machineinstrs (and possibly ↵Eli Friedman2011-09-07
| | | | | | | | | | fix some subtle bugs involving passes which check mayStore()). This isn't exactly ideal, but it is good enough for the moment. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139245 91177308-0d34-0410-b5e6-96231b3b80d8
* Codegen allonesvector better while using AVX: vpcmpeqd + vinsertf128Bruno Cardoso Lopes2011-07-25
| | | | | | This also fixes PR10452 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136004 91177308-0d34-0410-b5e6-96231b3b80d8
* Rename createAsmInfo to createMCAsmInfo and move registration code to ↵Evan Cheng2011-07-14
| | | | | | MCTargetDesc to prepare for next round of changes. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135219 91177308-0d34-0410-b5e6-96231b3b80d8
* Re-commit 131641 with fixes; de-pseudoize MOVSX16rr8 and friends.Stuart Hastings2011-05-20
| | | | | | | rdar://problem/8614450 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131746 91177308-0d34-0410-b5e6-96231b3b80d8
* Reverting 131641 to investigate 'bot complaint.Stuart Hastings2011-05-19
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131654 91177308-0d34-0410-b5e6-96231b3b80d8
* Revise MOVSX16rr8/MOVZX16rr8 (and rm variants) to no longer beStuart Hastings2011-05-19
| | | | | | | pseudos. rdar://problem/8614450 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131641 91177308-0d34-0410-b5e6-96231b3b80d8
* Add support for AVX to materialize +0.0 when doing scalar FP.Nate Begeman2010-12-09
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121415 91177308-0d34-0410-b5e6-96231b3b80d8
* Move lowering of TLS_addr32 and TLS_addr64 to X86MCInstLower.Rafael Espindola2010-11-28
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120263 91177308-0d34-0410-b5e6-96231b3b80d8
* tidy up, no functionality change.Chris Lattner2010-11-14
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119092 91177308-0d34-0410-b5e6-96231b3b80d8
* move the pic base symbol stuff up to MachineFunctionChris Lattner2010-11-14
| | | | | | | | since it is trivial and will be shared between ppc and x86. This substantially simplifies the X86 backend also. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119089 91177308-0d34-0410-b5e6-96231b3b80d8
* simplify getPICBaseSymbol a bit.Chris Lattner2010-11-14
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119088 91177308-0d34-0410-b5e6-96231b3b80d8
* handle X86::EH_RETURN64 and X86::EH_RETURN.Rafael Espindola2010-10-26
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117378 91177308-0d34-0410-b5e6-96231b3b80d8
* reapply: Use the new TB_NOT_REVERSABLE flag instead of specialChris Lattner2010-10-08
| | | | | | | | | | | reapply: reimplement the second half of the or/add optimization. We should now with no changes. Turns out that one missing "Defs = [EFLAGS]" can upset things a bit. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116040 91177308-0d34-0410-b5e6-96231b3b80d8
* reapply the patch reverted in r116033:Chris Lattner2010-10-08
| | | | | | | | | | "Reimplement (part of) the or -> add optimization. Matching 'or' into 'add'" With a critical fix: the add pseudos clobber EFLAGS. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116039 91177308-0d34-0410-b5e6-96231b3b80d8
* Revert "Reimplement (part of) the or -> add optimization. Matching 'or' intoDaniel Dunbar2010-10-08
| | | | | | 'add'", which seems to have broken just about everything. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116033 91177308-0d34-0410-b5e6-96231b3b80d8
* Revert "reimplement the second half of the or/add optimization. We should now",Daniel Dunbar2010-10-08
| | | | | | which depends on r116007, which I am about to revert. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116031 91177308-0d34-0410-b5e6-96231b3b80d8
* reimplement the second half of the or/add optimization. We should nowChris Lattner2010-10-08
| | | | | | | | | | | only end up emitting LEA instead of OR. If we aren't able to promote something into an LEA, we should never be emitting it as an ADD. Add some testcases that we emit "or" in cases where we used to produce an "add". git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116026 91177308-0d34-0410-b5e6-96231b3b80d8
* Reimplement (part of) the or -> add optimization. Matching 'or' into 'add'Chris Lattner2010-10-07
| | | | | | | | | | | | | | | | | | | | | is general goodness because it allows ORs to be converted to LEA to avoid inserting copies. However, this is bad because it makes the generated .s file less obvious and gives valgrind heartburn (tons of false positives in bitfield code). While the general fix should be in valgrind, we can at least try to avoid emitting ADD instructions that *don't* get promoted to LEA. This is more work because it requires introducing pseudo instructions to represents "add that knows the bits are disjoint", but hey, people really love valgrind. This fixes this testcase: https://bugs.kde.org/show_bug.cgi?id=242137#c20 the add r/i cases are coming next. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116007 91177308-0d34-0410-b5e6-96231b3b80d8
* Massive rewrite of MMX: Dale Johannesen2010-09-30
| | | | | | | | | | | | | | | | | | | | | The x86_mmx type is used for MMX intrinsics, parameters and return values where these use MMX registers, and is also supported in load, store, and bitcast. Only the above operations generate MMX instructions, and optimizations do not operate on or produce MMX intrinsics. MMX-sized vectors <2 x i32> etc. are lowered to XMM or split into smaller pieces. Optimizations may occur on these forms and the result casted back to x86_mmx, provided the result feeds into a previous existing x86_mmx operation. The point of all this is prevent optimizations from introducing MMX operations, which is unsafe due to the EMMS problem. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115243 91177308-0d34-0410-b5e6-96231b3b80d8
* Check in forgotten file. Should fix build.Dale Johannesen2010-09-08
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113409 91177308-0d34-0410-b5e6-96231b3b80d8
* More fixes for win64:Anton Korobeynikov2010-08-17
| | | | | | | | - Do not clobber al during variadic calls, this is AMD64 ABI-only feature - Emit wincall64, where necessary Patch by Cameron Esfahani! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111289 91177308-0d34-0410-b5e6-96231b3b80d8
* Don't attempt to SimplifyShortMoveForm in 64-bit mode.Eli Friedman2010-08-16
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111182 91177308-0d34-0410-b5e6-96231b3b80d8
* Define AVX 128-bit pattern versions of SET0PS/PD.Bruno Cardoso Lopes2010-08-12
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110937 91177308-0d34-0410-b5e6-96231b3b80d8
* Begin to support some vector operations for AVX 256-bit intructions. The longBruno Cardoso Lopes2010-08-12
| | | | | | | | | | | term goal here is to be able to match enough of vector_shuffle and build_vector so all avx intrinsics which aren't mapped to their own built-ins but to shufflevector calls can be codegen'd. This is the first (baby) step, support building zeroed vectors. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110897 91177308-0d34-0410-b5e6-96231b3b80d8
* Handle the pseudo in MCInstLower.Eric Christopher2010-08-05
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110359 91177308-0d34-0410-b5e6-96231b3b80d8
* X86MCInstLower now depends on AsmPrinter being around.Chris Lattner2010-07-22
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109154 91177308-0d34-0410-b5e6-96231b3b80d8
* add some rough support for making mcinst lowering work without anChris Lattner2010-07-21
| | | | | | | | | asmprinter or mangler around. This is option #B for killing off X86InstrInfo::GetInstSizeInBytes. Option #A (killing "needsexactsize") was sent for consideration to llvmdev. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109056 91177308-0d34-0410-b5e6-96231b3b80d8
* make asmprinter optional, even though passing in null will cause things to ↵Chris Lattner2010-07-20
| | | | | | explode right now. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108955 91177308-0d34-0410-b5e6-96231b3b80d8
* continue pushing dependencies around.Chris Lattner2010-07-20
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108952 91177308-0d34-0410-b5e6-96231b3b80d8
* reduce X86MCInstLower dependencies on asmprinter.Chris Lattner2010-07-20
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108950 91177308-0d34-0410-b5e6-96231b3b80d8
* pass around MF, not MMI.Chris Lattner2010-07-20
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108949 91177308-0d34-0410-b5e6-96231b3b80d8
* cleanups.Chris Lattner2010-07-20
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108947 91177308-0d34-0410-b5e6-96231b3b80d8
* move two asmprinter methods into the asmprinter .cpp file.Chris Lattner2010-07-20
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108945 91177308-0d34-0410-b5e6-96231b3b80d8
* fix a layering problem by moving the x86 implementationChris Lattner2010-07-19
of AsmPrinter and InstLowering into libx86 and out of the asmprinter subdirectory. Now X86/AsmPrinter just depends on MC stuff, not all of codegen and LLVM IR. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108782 91177308-0d34-0410-b5e6-96231b3b80d8
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