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path: root/lib/Target/X86/X86ScheduleAtom.td
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* Move late partial-unrolling thresholds into the processor definitionsHal Finkel2014-05-08
| | | | | | | | | | | | | | | | | | | | | | The old method used by X86TTI to determine partial-unrolling thresholds was messy (because it worked by testing target features), and also would not correctly identify the target CPU if certain target features were disabled. After some discussions on IRC with Chandler et al., it was decided that the processor scheduling models were the right containers for this information (because it is often tied to special uop dispatch-buffer sizes). This does represent a small functionality change: - For generic x86-64 (which uses the SB model and, thus, will get some unrolling). - For AMD cores (because they still currently use the SB scheduling model) - For Haswell (based on benchmarking by Louis Gerbarg, it was decided to bump the default threshold to 50; we're working on a test case for this). Otherwise, nothing has changed for any other targets. The logic, however, has been moved into BasicTTI, so other targets may now also opt-in to this functionality simply by setting LoopMicroOpBufferSize in their processor model definitions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208289 91177308-0d34-0410-b5e6-96231b3b80d8
* Adds support for Atom Silvermont (SLM) - -march=slmPreston Gurd2013-09-13
| | | | | | | | | | | | | | Implements Instruction scheduler latencies for Silvermont, using latencies from the Intel Silvermont Optimization Guide. Auto detects SLM. Turns on post RA scheduler when generating code for SLM. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190717 91177308-0d34-0410-b5e6-96231b3b80d8
* Update machine models. Specify buffer sizes for OOO processors.Andrew Trick2013-06-15
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184033 91177308-0d34-0410-b5e6-96231b3b80d8
* Machine Model: Add MicroOpBufferSize and resource BufferSize.Andrew Trick2013-06-15
| | | | | | | | | | | | | Replace the ill-defined MinLatency and ILPWindow properties with with straightforward buffer sizes: MCSchedMode::MicroOpBufferSize MCProcResourceDesc::BufferSize These can be used to more precisely model instruction execution if desired. Disabled some misched tests temporarily. They'll be reenabled in a few commits. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184032 91177308-0d34-0410-b5e6-96231b3b80d8
* Corrected Atom latencies for SSE SQRT instructions.Preston Gurd2013-05-07
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181346 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove IIC_DEFAULT from X86Schedule.tdJakob Stoklund Olesen2013-03-25
| | | | | | | | All the instructions tagged with IIC_DEFAULT had nothing in common, and we already have a NoItineraries class to represent untagged instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177937 91177308-0d34-0410-b5e6-96231b3b80d8
* MIsched: add an ILP window property to machine model.Andrew Trick2013-01-09
| | | | | | | | | | This was an experimental option, but needs to be defined per-target. e.g. PPC A2 needs to aggressively hide latency. I converted some in-order scheduling tests to A2. Hal is working on more test cases. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171946 91177308-0d34-0410-b5e6-96231b3b80d8
* I'm introducing a new machine model to simultaneously allow simpleAndrew Trick2012-07-07
| | | | | | | | | | | | | | | | | | | | | | | subtarget CPU descriptions and support new features of MachineScheduler. MachineModel has three categories of data: 1) Basic properties for coarse grained instruction cost model. 2) Scheduler Read/Write resources for simple per-opcode and operand cost model (TBD). 3) Instruction itineraties for detailed per-cycle reservation tables. These will all live side-by-side. Any subtarget can use any combination of them. Instruction itineraries will not change in the near term. In the long run, I expect them to only be relevant for in-order VLIW machines that have complex contraints and require a precise scheduling/bundling model. Once itineraries are only actively used by VLIW-ish targets, they could be replaced by something more appropriate for those targets. This tablegen backend rewrite sets things up for introducing MachineModel type #2: per opcode/operand cost model. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159891 91177308-0d34-0410-b5e6-96231b3b80d8
* X86 itinerary properties.Andrew Trick2012-06-05
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157981 91177308-0d34-0410-b5e6-96231b3b80d8
* whitespaceAndrew Trick2012-06-05
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157976 91177308-0d34-0410-b5e6-96231b3b80d8
* Added X86 Atom latencies to X86InstrMMX.td.Preston Gurd2012-05-11
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156615 91177308-0d34-0410-b5e6-96231b3b80d8
* Added X86 Atom latencies for instructions in X86InstrInfo.td.Preston Gurd2012-05-10
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156579 91177308-0d34-0410-b5e6-96231b3b80d8
* Adds Intel Atom scheduling latencies to X86InstrSystem.td.Preston Gurd2012-05-04
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156194 91177308-0d34-0410-b5e6-96231b3b80d8
* This patch continues the work of adding instruction latencies for X86 Atom,Preston Gurd2012-05-02
| | | | | | | | by providing the latencies for the instructions in X86InstrFPStack.td. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155996 91177308-0d34-0410-b5e6-96231b3b80d8
* This patch adds X86 instruction itineraries for non-pseudo opcodes inPreston Gurd2012-03-19
| | | | | | | | | | | | | X86InstrCompiler.td. It also adds –mcpu-generic to the legalize-shift-64.ll test so the test will pass if run on an Intel Atom CPU, which would otherwise produce an instruction schedule which differs from that which the test expects. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153033 91177308-0d34-0410-b5e6-96231b3b80d8
* Intel Atom instruction itineraries for mov sign extension and mov zero ↵Andrew Trick2012-02-29
| | | | | | | | extension. Patch by Tyler Nowicki! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151743 91177308-0d34-0410-b5e6-96231b3b80d8
* This patch adds instruction latencies for the SSE instructionsPreston Gurd2012-02-27
| | | | | | | | to the instruction scheduler for the Intel Atom. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151590 91177308-0d34-0410-b5e6-96231b3b80d8
* Emacs-tag and some comment fix for all ARM, CellSPU, Hexagon, MBlaze, ↵Jia Liu2012-02-18
| | | | | | MSP430, PPC, PTX, Sparc, X86, XCore. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150878 91177308-0d34-0410-b5e6-96231b3b80d8
* Instruction scheduling itinerary for Intel Atom.Andrew Trick2012-02-01
Adds an instruction itinerary to all x86 instructions, giving each a default latency of 1, using the InstrItinClass IIC_DEFAULT. Sets specific latencies for Atom for the instructions in files X86InstrCMovSetCC.td, X86InstrArithmetic.td, X86InstrControl.td, and X86InstrShiftRotate.td. The Atom latencies for the remainder of the x86 instructions will be set in subsequent patches. Adds a test to verify that the scheduler is working. Also changes the scheduling preference to "Hybrid" for i386 Atom, while leaving x86_64 as ILP. Patch by Preston Gurd! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149558 91177308-0d34-0410-b5e6-96231b3b80d8
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