llvm - Unofficial llvm GIT mirror used in EmbToolkit

	Commit message (Collapse)	Author	Age
*	[XCore] Add missing 2r instructions.	Richard Osborne	2013-02-17
\| \| \| \| \| \| \|	These instructions are not targeted by the compiler but it is needed for the MC layer. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175407 91177308-0d34-0410-b5e6-96231b3b80d8
*	[XCore] Add TSETR instruction.	Richard Osborne	2013-02-17
\| \| \| \| \| \| \|	This instruction is not targeted by the compiler but it is needed for the MC layer. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175406 91177308-0d34-0410-b5e6-96231b3b80d8
*	Add instruction encodings / disassembly support for l4r instructions.	Richard Osborne	2013-01-25
\| \| \| \|	git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173501 91177308-0d34-0410-b5e6-96231b3b80d8
*	Add instruction encodings / disassembly support for l5r instructions.	Richard Osborne	2013-01-25
\| \| \| \|	git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173479 91177308-0d34-0410-b5e6-96231b3b80d8
*	Add instruction encodings / disassembly support for l6r instructions.	Richard Osborne	2013-01-23
\| \| \| \|	git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173288 91177308-0d34-0410-b5e6-96231b3b80d8
*	Add instruction encodings / disassembly support for u10 / lu10 instructions.	Richard Osborne	2013-01-22
\| \| \| \|	git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173204 91177308-0d34-0410-b5e6-96231b3b80d8
*	Add instruction encodings / disassembly support for u6 / lu6 instructions.	Richard Osborne	2013-01-21
\| \| \| \|	git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173086 91177308-0d34-0410-b5e6-96231b3b80d8
*	Add instruction encoding / disassembly support for ru6 / lru6 instructions.	Richard Osborne	2013-01-21
\| \| \| \|	git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173085 91177308-0d34-0410-b5e6-96231b3b80d8
*	Add instruction encodings / disassembly support for l2rus instructions.	Richard Osborne	2013-01-20
\| \| \| \|	git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172987 91177308-0d34-0410-b5e6-96231b3b80d8
*	Add instruction encodings / disassembly support for l3r instructions.	Richard Osborne	2013-01-20
\| \| \| \|	git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172986 91177308-0d34-0410-b5e6-96231b3b80d8
*	Add instruction encodings / disassembler support for 2rus instructions.	Richard Osborne	2013-01-20
\| \| \| \|	git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172985 91177308-0d34-0410-b5e6-96231b3b80d8
*	Add instruction encodings / disassembly support 3r instructions.	Richard Osborne	2013-01-20
\| \| \| \| \| \| \| \|	It is not possible to distinguish 3r instructions from 2r / rus instructions using only the fixed bits. Therefore if an instruction doesn't match the 2r / rus format try to decode it as a 3r instruction before returning Fail. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172984 91177308-0d34-0410-b5e6-96231b3b80d8
*	Add instruction encodings / disassembly support for l2r instructions.	Richard Osborne	2012-12-17
\| \| \| \|	git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170345 91177308-0d34-0410-b5e6-96231b3b80d8
*	Add instruction encodings / disassembly support for rus instructions.	Richard Osborne	2012-12-17
\| \| \| \|	git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170330 91177308-0d34-0410-b5e6-96231b3b80d8
*	Add instruction encodings / disassembly support for 2r instructions.	Richard Osborne	2012-12-17
\| \| \| \|	git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170323 91177308-0d34-0410-b5e6-96231b3b80d8
*	Add instruction encodings / disassembly support for 0r instructions.	Richard Osborne	2012-12-17
\| \| \| \|	git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170322 91177308-0d34-0410-b5e6-96231b3b80d8
*	Add instruction encodings and disassembly for 1r instructions.	Richard Osborne	2012-12-16
\| \| \| \|	git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170293 91177308-0d34-0410-b5e6-96231b3b80d8
*	Remove invalid instruction encodings.	Richard Osborne	2012-12-16
\| \| \| \|	git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170291 91177308-0d34-0410-b5e6-96231b3b80d8
*	Mark anything deriving from PseudoInstXCore as a pseudo instruction.	Richard Osborne	2012-12-16
\| \| \| \|	git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170290 91177308-0d34-0410-b5e6-96231b3b80d8
*	Set instruction size correctly in XCoreInstrFormats.td	Richard Osborne	2012-12-16
\| \| \| \|	git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170289 91177308-0d34-0410-b5e6-96231b3b80d8
*	Emacs-tag and some comment fix for all ARM, CellSPU, Hexagon, MBlaze, ↵	Jia Liu	2012-02-18
\| \| \| \| \| \|	MSP430, PPC, PTX, Sparc, X86, XCore. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150878 91177308-0d34-0410-b5e6-96231b3b80d8
*	Add XCore backend.	Richard Osborne	2008-11-07
	git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58838 91177308-0d34-0410-b5e6-96231b3b80d8