summaryrefslogtreecommitdiff
path: root/lib/Target
Commit message (Expand)AuthorAge
* Most PPC M[TF]CR instructions do not have side effectsHal Finkel2013-04-07
* PPC pre-increment load instructions do not have side effectsHal Finkel2013-04-07
* PPC pre-increment load instructions do not have side effectsHal Finkel2013-04-07
* PPC MCRF instruction does not have side effectsHal Finkel2013-04-07
* PPC FMR instruction does not have side effectsHal Finkel2013-04-07
* Implement LowerReturn_64 for SPARC v9.Jakob Stoklund Olesen2013-04-06
* SPARC v9 stack pointer bias.Jakob Stoklund Olesen2013-04-06
* Implement PPCInstrInfo::FoldImmediateHal Finkel2013-04-06
* PPC ISEL is a select and never has side effectsHal Finkel2013-04-06
* Complete formal arguments for the SPARC v9 64-bit ABI.Jakob Stoklund Olesen2013-04-06
* R600/SI: Add support for buffer stores v2Tom Stellard2013-04-05
* R600/SI: Use same names for corresponding MUBUF operands and encoding fieldsTom Stellard2013-04-05
* R600: Add RV670 processorTom Stellard2013-04-05
* R600/SI: Add processor types for each SI variantTom Stellard2013-04-05
* R600/SI: Avoid generating S_MOVs with 64-bit immediates v2Tom Stellard2013-04-05
* Enable early if conversion on PPCHal Finkel2013-04-05
* Correct the PPC A2 misprediction penaltyHal Finkel2013-04-05
* Use the target options specified on a function to reset the back-end.Bill Wendling2013-04-05
* Reverting 178851 as it broke buildbotsRenato Golin2013-04-05
* [ms-inline asm] Add support for numeric displacement expressions in bracketedChad Rosier2013-04-05
* Buildbot fix for r178851: mistake was in wrong TargetRegisterInfo::getRegClas...Stepan Dyatkovskiy2013-04-05
* Fix for PR14824: "Optimization arm_ldst_opt inserts newly generated instructi...Stepan Dyatkovskiy2013-04-05
* Add a SchedMachineModel for the PPC G5Hal Finkel2013-04-05
* Add a SchedMachineModel for the PPC A2Hal Finkel2013-04-05
* ARM scheduler model: Add scheduler info to more instructions and resourceArnold Schwaighofer2013-04-05
* ARM scheduler model: Swift has varying latencies, uops for simple ALU opsArnold Schwaighofer2013-04-05
* X86 cost model: Differentiate cost for vector shifts of constantsArnold Schwaighofer2013-04-04
* CostModel: Add parameter to instruction cost to further classify operand valuesArnold Schwaighofer2013-04-04
* Rename the current PPC BCL definition to BCLalwaysHal Finkel2013-04-04
* PPC: Improve code generation for mixed-precision reciprocal sqrtHal Finkel2013-04-04
* Hexagon: Expand br_cc.Jyotsna Verma2013-04-04
* [XCore] Add bru instruction.Richard Osborne2013-04-04
* [XCore] The RRegs register class is a superset of GRRegs.Richard Osborne2013-04-04
* Avoid high-latency false CPSR dependencies even for tMOVSi.Jakob Stoklund Olesen2013-04-04
* R600: Use a mask for offsets when encoding instructionsVincent Lejeune2013-04-04
* R600: Fix wrong address when substituting ENDIFVincent Lejeune2013-04-04
* R600: Take export into account when computing cf addressVincent Lejeune2013-04-04
* Add SPARC v9 support for select on 64-bit compares.Jakob Stoklund Olesen2013-04-04
* X86 cost model: Vector shifts are expensive in most casesArnold Schwaighofer2013-04-03
* R600: Fix last ALU of a clause being emitted in a separate clauseVincent Lejeune2013-04-03
* Cleanup PPC reciprocal-estimate functionalityHal Finkel2013-04-03
* R600: Factorize maximum alu per clause in a single locationVincent Lejeune2013-04-03
* R600: Simplify data structure and add DEBUG to R600ControlFlowFinalizerVincent Lejeune2013-04-03
* R600: Consider KILLGT as an ALU instructionVincent Lejeune2013-04-03
* PPC: Enable FRES and FRSQRTE on the default PPC64 descriptionHal Finkel2013-04-03
* PPC: Add a FIXME regarding the non-working fma+fneg Altivec patternHal Finkel2013-04-03
* Remove some obsolete PowerPC/README entriesHal Finkel2013-04-03
* More direct types in PowerPC AltiVec intrinsics.Ulrich Weigand2013-04-03
* Fix PR15632: No support for ppcf128 floating-point remainder on PowerPC.Bill Schmidt2013-04-03
* AArch64: implement ETMv4 trace system registers.Tim Northover2013-04-03