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* Make some code a little simpler.Reed Kotler2013-01-28
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173649 91177308-0d34-0410-b5e6-96231b3b80d8
* [XCore] Add missing l2rus instructions.Richard Osborne2013-01-27
| | | | | | | These instructions are not targeted by the compiler but they are needed for the MC layer. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173634 91177308-0d34-0410-b5e6-96231b3b80d8
* [XCore] Add missing l2r instructions.Richard Osborne2013-01-27
| | | | | | | These instructions are not targeted by the compiler but they are needed for the MC layer. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173629 91177308-0d34-0410-b5e6-96231b3b80d8
* [XCore] Add missing 1r instructions.Richard Osborne2013-01-27
| | | | | | | These instructions are not targeted by the compiler but they are needed for the MC layer. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173624 91177308-0d34-0410-b5e6-96231b3b80d8
* [XCore] Add missing 0r instructions.Richard Osborne2013-01-27
| | | | | | | These instructions are not targeted by the compiler but they are needed for the MC layer. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173623 91177308-0d34-0410-b5e6-96231b3b80d8
* Convert the CPP backend to use the AttributeSet instead of AttributeWithIndex.Bill Wendling2013-01-27
| | | | | | | Further removal of the introspective AttributeWithIndex thing. Also fix the #includes. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173599 91177308-0d34-0410-b5e6-96231b3b80d8
* X86: Decode PALIGN operands so I don't have to do it in my head.Benjamin Kramer2013-01-26
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173572 91177308-0d34-0410-b5e6-96231b3b80d8
* X86: Do splat promotion later, so the optimizer can chew on it first.Benjamin Kramer2013-01-26
| | | | | | | | | | | | This catches many cases where we can emit a more efficient shuffle for a specific mask or when the mask contains undefs. Once the splat is lowered to unpacks we can't do that anymore. There is a possibility of moving the promotion after pshufb matching, but I'm not sure if pshufb with a mask loaded from memory is faster than 3 shuffles, so I avoided that for now. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173569 91177308-0d34-0410-b5e6-96231b3b80d8
* fix use of std::std. it's ordered set.Reed Kotler2013-01-26
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173563 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove unused variables, silences -Wunused-variableDmitri Gribenko2013-01-25
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173526 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove some introspection functions.Bill Wendling2013-01-25
| | | | | | | | | The 'getSlot' function and its ilk allow introspection into the AttributeSet class. However, that class should be opaque. Allow access through accessor methods instead. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173522 91177308-0d34-0410-b5e6-96231b3b80d8
* Initial implementation of PPCTargetTransformInfoHal Finkel2013-01-25
| | | | | | | | | | This provides a place to add customized operation cost information and control some other target-specific IR-level transformations. The only non-trivial logic in this checkin assigns a higher cost to unaligned loads and stores (covered by the included test case). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173520 91177308-0d34-0410-b5e6-96231b3b80d8
* In this patch, we teach X86_64TargetMachine that it has a ILP32Eli Bendersky2013-01-25
| | | | | | | | | | | | | | | | | | | | | | | (defined by the x32 ABI) mode, in which case its pointers are 32-bits in size. This knowledge is also added to X86RegisterInfo that now returns the appropriate registers in getPointerRegClass. There are many outcomes to this change. In order to keep the patches separate and manageable, we start by focusing on some simple testable cases. The patch adds a test with passing a pointer to a function - focusing on the difference between the two data models for x86-64. Another test is added for handling of 'sret' arguments (and functionality is added in X86ISelLowering to make it work). A note on naming: the "x32 ABI" document refers to the AMD64 architecture (in LLVM it's distinguished by being is64Bits() in the x86 subtarget) with two variations: the LP64 (default) data model, and the ILP32 data model. This patch adds predicates to the subtarget which are consistent with this naming scheme. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173503 91177308-0d34-0410-b5e6-96231b3b80d8
* Add instruction encodings / disassembly support for l4r instructions.Richard Osborne2013-01-25
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173501 91177308-0d34-0410-b5e6-96231b3b80d8
* Use the new 'getSlotIndex' method to retrieve the attribute's slot index.Bill Wendling2013-01-25
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173499 91177308-0d34-0410-b5e6-96231b3b80d8
* Use the correct format in the STW / SETPSC instruction names.Richard Osborne2013-01-25
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173494 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix order of operands for crc8_l4rRichard Osborne2013-01-25
| | | | | | | | The order in which operands appear in the encoded instruction is different to order in which they appear in assembly. This changes the XCore backend to use the instruction encoding order. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173493 91177308-0d34-0410-b5e6-96231b3b80d8
* Add instruction encodings / disassembly support for l5r instructions.Richard Osborne2013-01-25
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173479 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix order of operands for l5r instructions.Richard Osborne2013-01-25
| | | | | | | With this change the operands order matches the order in which the operands are encoded in the instruction. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173477 91177308-0d34-0410-b5e6-96231b3b80d8
* Use correct mnemonic / instruction name for ldivu.Richard Osborne2013-01-25
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173476 91177308-0d34-0410-b5e6-96231b3b80d8
* More cleanup of PPC register definitions.Hal Finkel2013-01-25
| | | | | | | Uses the new !add TableGen operator to do more cleanup of the PPC register definitions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173446 91177308-0d34-0410-b5e6-96231b3b80d8
* Fixed the condition codes for the atomic64 min/umin code generation on ARM. ↵Silviu Baranga2013-01-25
| | | | | | If the sutraction of the higher 32 bit parts gives a 0 result, we need to do the store operation. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173437 91177308-0d34-0410-b5e6-96231b3b80d8
* MIsched: Improve the interface to SchedDFS analysis (subtrees).Andrew Trick2013-01-25
| | | | | | | Allow the strategy to select SchedDFS. Allow the results of SchedDFS to affect initialization of the scheduler state. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173425 91177308-0d34-0410-b5e6-96231b3b80d8
* This patch implements parsing the .wordJack Carter2013-01-25
| | | | | | | | | | directive for the Mips assembler. Contributer: Vladimir Medic git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173407 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips] Set flag neverHasSideEffects flag on some of the floating point ↵Akira Hatanaka2013-01-25
| | | | | | instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173401 91177308-0d34-0410-b5e6-96231b3b80d8
* Moving Cost Tables up to share with other targetsRenato Golin2013-01-24
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173382 91177308-0d34-0410-b5e6-96231b3b80d8
* Start cleanup of PPC register definitions using foreach loops.Hal Finkel2013-01-24
| | | | | | | | | | | No functionality change intended. This captures the first two cases GPR32/64. For the others, we need an addition operator (if we have one, I've not yet found it). Based on a suggestion made by Tom Stellard in the AArch64 review! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173366 91177308-0d34-0410-b5e6-96231b3b80d8
* MipsISelLowering.cpp: Fill unreachable paths to fix warnings. ↵NAKAMURA Takumi2013-01-24
| | | | | | | | | [-Wsometimes-uninitialized] FIXME: Could they, unreachable(s), be removed? FIXME: I could prefer the coding standards... git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173325 91177308-0d34-0410-b5e6-96231b3b80d8
* MipsISelLowering.cpp: Fix a warning, take two. [-Wunused-variable]NAKAMURA Takumi2013-01-24
| | | | | | ...and fix a typo, s/#ifdef/#ifndef/ git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173324 91177308-0d34-0410-b5e6-96231b3b80d8
* MipsISelLowering.cpp: Fix a warning. [-Wunused-variable]NAKAMURA Takumi2013-01-24
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173323 91177308-0d34-0410-b5e6-96231b3b80d8
* The next phase of Mips16 hard float implementation.Reed Kotler2013-01-24
| | | | | | | | | | | | | | | | | | Allow Mips16 routines to call Mips32 routines that have abi requirements that either arguments or return values are passed in floating point registers. This handles only the pic case. We have not done non pic for Mips16 yet in any form. The libm functions are Mips32, so with this addition we have a complete Mips16 hard float implementation. We still are not able to complete mix Mip16 and Mips32 with hard float. That will be the next phase which will have several steps. For Mips32 to freely call Mips16 some stub functions must be created. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173320 91177308-0d34-0410-b5e6-96231b3b80d8
* R600: Add a llvm.R600.store.swizzle intrinsicsTom Stellard2013-01-23
| | | | | | | | | | | This intrinsic is translated to ALLOC_EXPORT_WORD1_SWIZ, hence its name. It is used to store vs/fs outputs Patch by: Vincent Lejeune Reviewed-by: Tom Stellard <thomas.stellard@amd.com> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173297 91177308-0d34-0410-b5e6-96231b3b80d8
* R600: Simplify stream outputs intrinsicTom Stellard2013-01-23
| | | | | | | | Patch by: Vincent Lejeune Reviewed-by: Tom Stellard <thomas.stellard@amd.com> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173296 91177308-0d34-0410-b5e6-96231b3b80d8
* Add instruction encodings / disassembly support for l6r instructions.Richard Osborne2013-01-23
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173288 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix powerpc test failure - forgot to initialize stack slot size for ↵Eli Bendersky2013-01-23
| | | | | | PPCLinuxMCAsmInfo git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173275 91177308-0d34-0410-b5e6-96231b3b80d8
* Clean up assignment of CalleeSaveStackSlotSize: get rid of the default and ↵Eli Bendersky2013-01-23
| | | | | | explicitly set this in every target that needs to change it from the default. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173270 91177308-0d34-0410-b5e6-96231b3b80d8
* NVPTX: Stop leaking memory by using a managed constant instead of a new ↵Benjamin Kramer2013-01-23
| | | | | | | | | Argument. This is still an egregious hack since we don't have a nice interface for this kind of thing but should help the valgrind leak check buildbot to become green. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173267 91177308-0d34-0410-b5e6-96231b3b80d8
* Add the IR attribute 'sspstrong'.Bill Wendling2013-01-23
| | | | | | | | | | | | | | | | | | | | | | SSPStrong applies a heuristic to insert stack protectors in these situations: * A Protector is required for functions which contain an array, regardless of type or length. * A Protector is required for functions which contain a structure/union which contains an array, regardless of type or length. Note, there is no limit to the depth of nesting. * A protector is required when the address of a local variable (i.e., stack based variable) is exposed. (E.g., such as through a local whose address is taken as part of the RHS of an assignment or a local whose address is taken as part of a function argument.) This patch implements the SSPString attribute to be equivalent to SSPRequired. This will change in a subsequent patch. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173230 91177308-0d34-0410-b5e6-96231b3b80d8
* R600: rework handling of the constantsTom Stellard2013-01-23
| | | | | | | | | | | | | | | | | | | | | Remove Cxxx registers, add new special register - "ALU_CONST" and new operand for each alu src - "sel". ALU_CONST is used to designate that the new operand contains the value to override src.sel, src.kc_bank, src.chan for constants in the driver. Patch by: Vadim Girlin Vincent Lejeune: - Use pointers for constants - Fold CONST_ADDRESS when possible Tom Stellard: - Give CONSTANT_BUFFER_0 its own address space - Use integer types for constant loads Reviewed-by: Tom Stellard <thomas.stellard@amd.com> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173222 91177308-0d34-0410-b5e6-96231b3b80d8
* R600: Add a CONST_ADDRESS node to model constant buf readTom Stellard2013-01-23
| | | | | | | | Patch by: Vincent Lejeune Reviewed-by: Tom Stellard <thomas.stellard@amd.com> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173221 91177308-0d34-0410-b5e6-96231b3b80d8
* R600: Factorise VTX_WORD0 and VTX_WORD1 in tblgen defTom Stellard2013-01-23
| | | | | | | | Patch by: Vincent Lejeune Reviewed-by: Tom Stellard <thomas.stellard@amd.com> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173220 91177308-0d34-0410-b5e6-96231b3b80d8
* Add instruction encodings / disassembly support for u10 / lu10 instructions.Richard Osborne2013-01-22
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173204 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix an issue of pseudo atomic instruction DAG scheduleMichael Liao2013-01-22
| | | | | | | | | | | | - Add list of physical registers clobbered in pseudo atomic insts Physical registers are clobbered when pseudo atomic instructions are expanded. Add them in clobber list to prevent DAG scheduler to mis-schedule them after these insns are declared side-effect free. - Add test case from Michael Kuperstein <michael.m.kuperstein@intel.com> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173200 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips] Implement MipsRegisterInfo::getRegPressureLimit.Akira Hatanaka2013-01-22
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173197 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips] Clean up code in MipsTargetLowering::LowerCall. No functional changeAkira Hatanaka2013-01-22
| | | | | | | | intended git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173189 91177308-0d34-0410-b5e6-96231b3b80d8
* X86: Make sure we account for the FMA4 register immediate value, otherwise ↵Benjamin Kramer2013-01-22
| | | | | | | | rip-rel relocations will be off by one byte. PR15040. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173176 91177308-0d34-0410-b5e6-96231b3b80d8
* Initial patch for x32 ABI support.Eli Bendersky2013-01-22
| | | | | | | | | | Add the x32 environment kind to the triple, and separate the concept of pointer size and callee save stack slot size, since they're not equal on x32. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173175 91177308-0d34-0410-b5e6-96231b3b80d8
* Make APFloat constructor require explicit semantics.Tim Northover2013-01-22
| | | | | | | | | Previously we tried to infer it from the bit width size, with an added IsIEEE argument for the PPC/IEEE 128-bit case, which had a default value. This default value allowed bugs to creep in, where it was inappropriate. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173138 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix some incorrectly named u10 / lu10 instructions.Richard Osborne2013-01-21
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173090 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove unused multiclass.Richard Osborne2013-01-21
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173087 91177308-0d34-0410-b5e6-96231b3b80d8
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