| Commit message (Expand) | Author | Age |
|---|
| * | Re-applying the target data layout verification patch from r142288, plus appr... | Lang Hames | 2011-10-17 |
| * | ARM assembly parsing and encoding for VMOV/VMVN/VORR/VBIC.i16. | Jim Grosbach | 2011-10-17 |
| * | Add support for a new extension to the .file directive: | Nick Lewycky | 2011-10-17 |
| * | Add a few FIXME comments. | Chad Rosier | 2011-10-17 |
| * | Tidy up. | Jim Grosbach | 2011-10-17 |
| * | 142288 broke the build: | Rafael Espindola | 2011-10-17 |
| * | Now Igor, throw the switch...give my creation life! | Bill Wendling | 2011-10-17 |
| * | ARM NEON "vmov.i8" immediate assembly parsing and encoding. | Jim Grosbach | 2011-10-17 |
| * | Validate target data layout strings. | Lang Hames | 2011-10-17 |
| * | Use a SmallVector for intrinsic argument types. | Benjamin Kramer | 2011-10-17 |
| * | Don't renumber the blocks here. This could cause problems later on if another | Bill Wendling | 2011-10-17 |
| * | Pseudoinstructions should not be less constrained than the instruction they are | Cameron Zwarich | 2011-10-17 |
| * | Tidy up organization. | Jim Grosbach | 2011-10-17 |
| * | Add a call to EmitSjLjDispatchBlock. | Bill Wendling | 2011-10-17 |
| * | Fix improperly formed assert() call. | Jim Grosbach | 2011-10-17 |
| * | Add definitions of conditional moves with 64-bit operands. Comment out code for | Akira Hatanaka | 2011-10-17 |
| * | Revert change to function alignment b/c existing logic was fine | Hal Finkel | 2011-10-17 |
| * | Removed set, but unused variables. | Chad Rosier | 2011-10-17 |
| * | Move class and instruction definitions for conditional moves to a seperate file. | Akira Hatanaka | 2011-10-17 |
| * | Revert change made in r142205. | Akira Hatanaka | 2011-10-17 |
| * | Redefine count-leading 0s and 1s instructions. | Akira Hatanaka | 2011-10-17 |
| * | Redefine mfhi/lo and mthi/lo instructions. | Akira Hatanaka | 2011-10-17 |
| * | Redefine multiply and divide instructions. | Akira Hatanaka | 2011-10-17 |
| * | Add definition of a base class for logical shift/rotate instructions with two | Akira Hatanaka | 2011-10-17 |
| * | Remove >80-col line and unicode | Hal Finkel | 2011-10-17 |
| * | Add definition of a base class for logical shift/rotate immediate instructions | Akira Hatanaka | 2011-10-17 |
| * | Add definition of immZExt5_64 and redefine immZExt5 as an ImmLeaf. | Akira Hatanaka | 2011-10-17 |
| * | Fix CMake build. | Michael J. Spencer | 2011-10-17 |
| * | svn mv Target/ARM/ARMGlobalMerge.cpp Transforms/Scalar/GlobalMerge.cpp | Devang Patel | 2011-10-17 |
| * | Instructions for Book E PPC should be word aligned, set function alignment to... | Hal Finkel | 2011-10-17 |
| * | Don't use inline assembly in 64-bit Visual Studio. Unfortunately, this means ... | Craig Topper | 2011-10-17 |
| * | Add comment explaining that the order of processing doesn't matter here. | Bill Wendling | 2011-10-17 |
| * | Add PPC 440 scheduler and some associated tests (new files) | Hal Finkel | 2011-10-17 |
| * | Add PPC 440 scheduler and some associated tests | Hal Finkel | 2011-10-17 |
| * | Add X86 PEXTR and PDEP instructions. | Craig Topper | 2011-10-16 |
| * | Add AsmToken::getEndLoc and use it to add ranges to x86 asm register parsing. | Benjamin Kramer | 2011-10-16 |
| * | X86AsmParser: Synthesize EndLoc for tokens out of StartLoc + Length and print... | Benjamin Kramer | 2011-10-16 |
| * | Fix a bug in LowerV2I64Splat, which generated a BUILD_VECTOR for which there was | Nadav Rotem | 2011-10-16 |
| * | Add X86 BZHI instruction as well as BMI2 feature detection. | Craig Topper | 2011-10-16 |
| * | Add X86 INVPCID instruction. Add 32/64-bit predicates to INVEPT, INVVPID, VMR... | Craig Topper | 2011-10-16 |
| * | Add flags on Thumb2 indexed stores paralleling the flags on the indexed loads. | Cameron Zwarich | 2011-10-16 |
| * | Fix an obvious typo found when looking at nearby code. | Cameron Zwarich | 2011-10-16 |
| * | Enhance llvm::SourceMgr to support diagnostic ranges, the same way clang does... | Chris Lattner | 2011-10-16 |
| * | Add X86 BEXTR instruction. This instruction uses VEX.vvvv to encode Operand 3... | Craig Topper | 2011-10-16 |
| * | Add X86 feature detection support for BMI instructions. Added new cpuid funct... | Craig Topper | 2011-10-16 |
| * | Add support for X86 blsr, blsmsk, and blsi instructions. Required extra work ... | Craig Topper | 2011-10-15 |
| * | The CELL backend cannot select patterns for vector trunc-store and shl on v2... | Nadav Rotem | 2011-10-15 |
| * | ARM cannot select a pattern for trunc-store v4i8; /ARM/vrev.ll fails when pro... | Nadav Rotem | 2011-10-15 |
| * | SmallVector -> array | Benjamin Kramer | 2011-10-15 |
| * | Mark tADDrSPi as having side effects again. | Jakob Stoklund Olesen | 2011-10-15 |
