| Commit message (Expand) | Author | Age |
|---|
| * | [C++11] Replace OwningPtr with std::unique_ptr in places where it doesn't bre... | Benjamin Kramer | 2014-04-21 |
| * | [X86] ISEL (and X, <constant mask>) to BZHI when BMI2 is available. | Lang Hames | 2014-04-21 |
| * | Revert r206732 which is causing llc to crash on most of the build bots. | Chandler Carruth | 2014-04-21 |
| * | Implement builtins for safe division: safe.sdiv.iN, safe.udiv.iN, safe.srem.iN, | Michael Zolotukhin | 2014-04-21 |
| * | C++ has a bool type! (And C's had one too, for 15 years...) | Richard Smith | 2014-04-20 |
| * | More C++ification. | Richard Smith | 2014-04-20 |
| * | Remove some more C junk from these files. | Richard Smith | 2014-04-20 |
| * | Don't provide two different definitions of ModRMDecision, OpcodeDecision, and... | Richard Smith | 2014-04-20 |
| * | Don't define llvm::X86Disassembler::InstructionSpecifier in different ways in | Richard Smith | 2014-04-20 |
| * | Maybe if I touch this file the buildbots will actually rerun configure like t... | Richard Smith | 2014-04-20 |
| * | What year is it! This file has no reason to be written in C, and has doubly no | Richard Smith | 2014-04-20 |
| * | Remove some empty statements | Alp Toker | 2014-04-19 |
| * | Patch by Vadim Chugunov | Yaron Keren | 2014-04-19 |
| * | Change the ARM assembler to require a :lower16: or :upper16 on non-constant | Kevin Enderby | 2014-04-18 |
| * | [ARM64] Ports the Cortex-A53 Machine Model description from AArch64. | Chad Rosier | 2014-04-18 |
| * | [X86] Improve buildFromShuffleMostly for AVX | Adam Nemet | 2014-04-18 |
| * | ARM64: disable generation of .loh directives outside MachO. | Tim Northover | 2014-04-18 |
| * | ARM64: don't emit .subsections_via_symbols on ELF. | Tim Northover | 2014-04-18 |
| * | ARM64: add extra NEG pattern. | Tim Northover | 2014-04-18 |
| * | AArch64/ARM64: add non-scalar lowering for more FCVT operations. | Tim Northover | 2014-04-18 |
| * | AArch64/ARM64: improve spotting of EXT instructions from VECTOR_SHUFFLE. | Tim Northover | 2014-04-18 |
| * | X86: Pattern match scalar loads + vcvtph2ps into just vcvtph2ps. | Benjamin Kramer | 2014-04-18 |
| * | AArch64/ARM64: spot a greater variety of concat_vector operations. | Tim Northover | 2014-04-18 |
| * | ARM64: implement cunning optimisation from AArch64 | Tim Northover | 2014-04-18 |
| * | ARM64: spot a vector_shuffle that maps to INS and expand. | Tim Northover | 2014-04-18 |
| * | ARM64: nick some AArch64 patterns for extract/insert -> INS. | Tim Northover | 2014-04-18 |
| * | AArch64/ARM64: emit all vector FP comparisons as such. | Tim Northover | 2014-04-18 |
| * | AArch64/ARM64: port BSL logic from AArch64 & enable test. | Tim Northover | 2014-04-18 |
| * | AArch64/ARM64: copy byval implementation from AArch64. | Tim Northover | 2014-04-18 |
| * | This commit allows vectorized loops to be unrolled by a factor of 2 for AArch64. | Jiangning Liu | 2014-04-18 |
| * | R600: Minor cleanups. | Matt Arsenault | 2014-04-18 |
| * | This is one of the optimizations ported from ARM64 to AArch64 to address the ... | Jiangning Liu | 2014-04-18 |
| * | R600/SI: Try to use scalar BFE. | Matt Arsenault | 2014-04-18 |
| * | This commit enables unaligned memory accesses of vector types on AArch64 back... | Jiangning Liu | 2014-04-18 |
| * | R600/SI: Match sign_extend_inreg to s_sext_i32_i8 and s_sext_i32_i16 | Matt Arsenault | 2014-04-18 |
| * | R600/SI: Use SReg_64 instead of VSrc_64 when selecting BUILD_PAIR | Tom Stellard | 2014-04-18 |
| * | [ARM64,C++11] Range'ify another loop. | Jim Grosbach | 2014-04-17 |
| * | Start pushing changes for Mips Fast-Isel | Reed Kotler | 2014-04-17 |
| * | R600: Add comment clariying use of sext for result of MUL_U24 | Tom Stellard | 2014-04-17 |
| * | R600/SI: Stop using i128 as the resource descriptor type | Tom Stellard | 2014-04-17 |
| * | R600/SI: Change default register class for i32 to SReg_32 | Tom Stellard | 2014-04-17 |
| * | R600/SI: Teach SIInstrInfo::moveToVALU() how to handle PHI instructions | Tom Stellard | 2014-04-17 |
| * | R600/SI: Legalize operands after changing dst reg in FixSGPRCopies | Tom Stellard | 2014-04-17 |
| * | Improve ARM64 vector creation | Louis Gerbarg | 2014-04-17 |
| * | ARM64: [su]xtw use W regs as inputs, not X regs. | Jim Grosbach | 2014-04-17 |
| * | ARM64: switch to IR-based atomic operations. | Tim Northover | 2014-04-17 |
| * | ARM64: add acquire/release versions of the existing atomic intrinsics. | Tim Northover | 2014-04-17 |
| * | Atomics: promote ARM's IR-based atomics pass to CodeGen. | Tim Northover | 2014-04-17 |
| * | R600/SI: f64 frint is legal on CI | Matt Arsenault | 2014-04-17 |
| * | [AArch64] Implement the getCSRFirstUseCost API, mirroring that in ARM64. | Chad Rosier | 2014-04-17 |
