| Commit message (Expand) | Author | Age |
|---|
| * | Implement depth_first and inverse_depth_first range factory functions. | David Blaikie | 2014-04-11 |
| * | [ARM64,C++11] Range'ify use-lists iterators in address type promotion. | Jim Grosbach | 2014-04-11 |
| * | [ARM64,C++11]: Range'ify use-list iterators in DAGToDAG. | Jim Grosbach | 2014-04-11 |
| * | [ARM64,C++11]: More range-based loop simplification. | Jim Grosbach | 2014-04-11 |
| * | Move the segmented stack switch to a function attribute | Reid Kleckner | 2014-04-10 |
| * | [ARM64,C++11]: Range'ify loops in InstrInfo. | Jim Grosbach | 2014-04-10 |
| * | [ARM64,C++11]: Range'ify loops in the conditional-compare pass. | Jim Grosbach | 2014-04-10 |
| * | For the ARM integrated assembler add checking of the | Kevin Enderby | 2014-04-10 |
| * | [mips] NotMips64 predicate is really a test for 32-bit GPR's. | Daniel Sanders | 2014-04-10 |
| * | [mips] Switch the MIPS-III and MIPS-IV assembler tests to use -mcpu=mips4. | Daniel Sanders | 2014-04-10 |
| * | ARM64/*/LLVMBuild.txt: Prune redundant deps. | NAKAMURA Takumi | 2014-04-10 |
| * | LLVMBuild.txt: Add missing dependencies. | NAKAMURA Takumi | 2014-04-10 |
| * | LLVMBuild.txt: Reformat. | NAKAMURA Takumi | 2014-04-10 |
| * | Fix abuse of StringRef on ARM64SysReg::MRSMapper::toString(Val, Valid). | NAKAMURA Takumi | 2014-04-10 |
| * | ARM64: add an explicit cast to silence a silly warning | Saleem Abdulrasool | 2014-04-10 |
| * | [ARM64] Fix immediate cost calculation for types larger than i64. | Juergen Ributzka | 2014-04-10 |
| * | Revert "For the ARM integrated assembler add checking of the alignments on vl... | Reid Kleckner | 2014-04-10 |
| * | Add support for load folding of avx1 logical instructions | Jim Grosbach | 2014-04-09 |
| * | For the ARM integrated assembler add checking of the | Kevin Enderby | 2014-04-09 |
| * | [AArch64] Implement the isZExtFree APIs. | Chad Rosier | 2014-04-09 |
| * | [AArch64] Implement the isTruncateFree API. | Chad Rosier | 2014-04-09 |
| * | Simple fix for build failures resulting from r205867. | Bob Wilson | 2014-04-09 |
| * | [NVPTX] Add preliminary intrinsics and codegen support for textures/surfaces | Justin Holewinski | 2014-04-09 |
| * | [NVPTX] Add support for addrspacecast in global variable initializers, includ... | Justin Holewinski | 2014-04-09 |
| * | [NVPTX] Add query support for read-write images and managed variables | Justin Holewinski | 2014-04-09 |
| * | Fix some doc and comment typos | Alp Toker | 2014-04-09 |
| * | [ARM64] Change SYS without a register to an alias to make disassembling more ... | Bradley Smith | 2014-04-09 |
| * | [ARM64] Correctly disassemble ISB operand as ISB not DBarrier. | Bradley Smith | 2014-04-09 |
| * | [ARM64] Properly support both apple and standard syntax for FMOV | Bradley Smith | 2014-04-09 |
| * | [ARM64] Flag setting logical/add/sub immediate instructions don't use SP. | Bradley Smith | 2014-04-09 |
| * | [ARM64] Conditional branches must always print their condition code, even AL. | Bradley Smith | 2014-04-09 |
| * | [ARM64] Fix disassembly logic for extended loads/stores with 32-bit registers. | Bradley Smith | 2014-04-09 |
| * | [ARM64] When printing a pre-indexed address with #0, the ', #0' is not optional. | Bradley Smith | 2014-04-09 |
| * | [ARM64] Add missing shifted register MVN alias to ORN | Bradley Smith | 2014-04-09 |
| * | [ARM64] SXTW/UXTW are only valid aliases for 32-bit operations. | Bradley Smith | 2014-04-09 |
| * | [ARM64] Fix canonicalisation of MOVs. MOV is too complex to be modelled by a ... | Bradley Smith | 2014-04-09 |
| * | [ARM64] Fixup ADR/ADRP parsing such that they accept immediates and all label... | Bradley Smith | 2014-04-09 |
| * | [ARM64] Ensure sp is decoded as SP, not XZR in LD1 instructions. | Bradley Smith | 2014-04-09 |
| * | [ARM64] Tighten up the special casing in emitting arithmetic extends. UXTW sh... | Bradley Smith | 2014-04-09 |
| * | [ARM64] Rename LR to the UAL-compliant 'X30'. | Bradley Smith | 2014-04-09 |
| * | [ARM64] Rename FP to the UAL-compliant 'X29'. | Bradley Smith | 2014-04-09 |
| * | [ARM64] Add a PostEncoderMethod to FCMP - the Rm field should canonically be ... | Bradley Smith | 2014-04-09 |
| * | [ARM64] SCVTF and FCVTZS/U are undefined if scale<5> == 0. | Bradley Smith | 2014-04-09 |
| * | [ARM64] EXT and EXTR instructions on v8i8 and W regs respectively must have t... | Bradley Smith | 2014-04-09 |
| * | [ARM64] Scaled fixed-point FCVTZSs should also have bit 29 set to zero. | Bradley Smith | 2014-04-09 |
| * | [ARM64] UBFM/BFM is undefined on w registers when imms<5> or immr<5> is 1. | Bradley Smith | 2014-04-09 |
| * | [ARM64] Floating point to fixed point scaled conversions are only available o... | Bradley Smith | 2014-04-09 |
| * | [ARM64] Port over the PostEncoderMethod fix for SMULH/UMULH from AArch64. | Bradley Smith | 2014-04-09 |
| * | [ARM64] Add missing tlbi operands and error for extra/missing register on tlb... | Bradley Smith | 2014-04-09 |
| * | [ARM64] Rework system register parsing to overcome SPSel clash in MSR variants. | Bradley Smith | 2014-04-09 |
