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* Revert r201237+r201238: Demote EmitRawText call in AsmPrinter::EmitInlineAsm(...Daniel Sanders2014-02-12
* Demote EmitRawText call in AsmPrinter::EmitInlineAsm() and remove hasRawTextS...Daniel Sanders2014-02-12
* R600: Always implement both versions of isTruncateFree and add a sanity check.Benjamin Kramer2014-02-12
* Mark XACQUIRE_PREFIX/XRELEASE_PREFIX as isAsmParserOnly so they'll disappear ...Craig Topper2014-02-12
* Tweak ARM fastcc by adopting these two AAPCS rules:Evan Cheng2014-02-11
* R600/SI: Fix assertion on infinite loops.Matt Arsenault2014-02-11
* ARM: Thumb2 LDR(literal) can target SP.Jim Grosbach2014-02-11
* XCore target: fix const section handlingRobert Lytton2014-02-11
* XCore target: Lower ATOMIC_LOAD & ATOMIC_STORERobert Lytton2014-02-11
* AVX: fixed a bug in LowerVECTOR_SHUFFLEElena Demikhovsky2014-02-11
* AVX-512: Optimized BUILD_VECTOR pattern; Elena Demikhovsky2014-02-11
* R600: Implement isTruncateFreeMatt Arsenault2014-02-10
* R600/SI: Initialize M0 and emit S_WQM_B64 whenever DS instructions are usedTom Stellard2014-02-10
* R600/SI: Only use S_WQM_B64 in pixel shadersTom Stellard2014-02-10
* ARM: use natural LLVM IR for vshll instructionsTim Northover2014-02-10
* [AArch64] Handle aliases of conditional branches without b.pred form.Chad Rosier2014-02-10
* ARM: r12 is callee-saved for interrupt handlersOliver Stannard2014-02-10
* ARM: use LLVM IR to represent the vshrn operationTim Northover2014-02-10
* [mips][msa] Add DLSA instruction.Matheus Almeida2014-02-10
* [mips][msa] Make LSA_DESC a parameterizable class.Matheus Almeida2014-02-10
* AVX-512: Fixed extract_vector_elt for v16i1 and v8i1 vectors.Elena Demikhovsky2014-02-10
* Recommit r201059 and r201060 with hopefully a fix for its original failure.Craig Topper2014-02-10
* Revert r201059 and r201060.Bob Wilson2014-02-10
* [AArch64]Implement the copy of two FPR8 registers by using FMOVss of two FPR3...Hao Liu2014-02-10
* Add MRMXr/MRMXm form to X86 for use by instructions which treat the 'reg' fie...Craig Topper2014-02-10
* Use a consistent argument order in TargetLoweringObjectFile.Rafael Espindola2014-02-09
* Pass the Mangler by reference.Rafael Espindola2014-02-08
* Add LLVM_OVERRIDE to a few declarations.Rafael Espindola2014-02-08
* Remove dead code.Rafael Espindola2014-02-07
* Remove -arm-disable-ehabi optionRenato Golin2014-02-07
* [mips] Forbid the use of registers t6, t7 and t8 if the target is NaCl.Sasa Stankovic2014-02-07
* LLVM-1163: AAPCS-VFP violation when CPRC allocated to stackOliver Stannard2014-02-07
* [Sparc] Add support for parsing synthetic instruction 'mov'. Venkatraman Govindaraju2014-02-07
* [Sparc] Emit correct encoding for atomic instructions. Also, add support for ...Venkatraman Govindaraju2014-02-07
* [Sparc] Emit relocations for Thread Local Storage (TLS) when integrated assem...Venkatraman Govindaraju2014-02-07
* [Sparc] Emit correct relocations for PIC code when integrated assembler is used.Venkatraman Govindaraju2014-02-07
* [Sparc] Use SparcMCExpr::VariantKind itself as MachineOperand's target flags.Venkatraman Govindaraju2014-02-07
* X86: Resolve a long standing FIXME and properly isel pextr[bw].Jim Grosbach2014-02-07
* Revert r200095 and r200152. It turns out when compiling with -arch armv7 -mcp...Evan Cheng2014-02-06
* R600/SI: Add a MUBUF store pattern for Reg+Imm offsetsTom Stellard2014-02-06
* R600/SI: Add a MUBUF store pattern for Imm offsetsTom Stellard2014-02-06
* R600/SI: Add a MUBUF load pattern for Reg+Imm offsetsTom Stellard2014-02-06
* R600/SI: Use immediates offsets for SMRD instructions whenever possibleTom Stellard2014-02-06
* Remove const_cast for STI when parsing inline asmDavid Peixotto2014-02-06
* X86: add costs for 64-bit vector ext/trunc & rebalanceTim Northover2014-02-06
* X86: deduplicate V[SZ]EXT_MOVL and V[SZ]EXT nodesTim Northover2014-02-06
* Update the X86 assembler for .intel_syntax to acceptKevin Enderby2014-02-06
* don't set HasReliableSymbolDifference for ELF.Rafael Espindola2014-02-06
* doesSectionRequireSymbols is meaningless on ELF, remove.Rafael Espindola2014-02-06
* Just returning false is the default.Rafael Espindola2014-02-06
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