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* [PM] Rename the IR printing pass header to a more generic and correctChandler Carruth2014-01-12
| | | | | | | | name to match the source file which I got earlier. Update the include sites. Also modernize the comments in the header to use the more recommended doxygen style. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199041 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM IAS: fix diagnostics of improper qualificationSaleem Abdulrasool2014-01-12
| | | | | | | | An improper qualifier would result in a superfluous error due to the parser not consuming the remainder of the statement. Simply consume the remainder of the statement to avoid the error. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199035 91177308-0d34-0410-b5e6-96231b3b80d8
* [Sparc] Add support for parsing floating point instructions.Venkatraman Govindaraju2014-01-12
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199033 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM: change implicit immediate forms of {ld,st}r{,b}t to psuedo-instructionsSaleem Abdulrasool2014-01-12
| | | | | | | | | | | | | The implicit immediate 0 forms are assembly aliases, not distinct instruction encodings. Fix the initial implementation introduced in r198914 to an alias to avoid two separate instruction definitions for the same encoding. An InstAlias is insufficient in this case as the necessary due to the need to add a new additional operand for the implicit zero. By using the AsmPsuedoInst, fall back to the C++ code to transform the instruction to the equivalent _POST_IMM form, inserting the additional implicit immediate 0. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199032 91177308-0d34-0410-b5e6-96231b3b80d8
* [Sparc] Replace (unsigned)-1 with ~OU as suggested by Reid Kleckner.Venkatraman Govindaraju2014-01-12
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199031 91177308-0d34-0410-b5e6-96231b3b80d8
* The SPARCv9 ABI returns a float in %f0.Jakob Stoklund Olesen2014-01-12
| | | | | | | | | | | | | | | This is different from the argument passing convention which puts the first float argument in %f1. With this patch, all returned floats are treated as if the 'inreg' flag were set. This means multiple float return values get packed in %f0, %f1, %f2, ... Note that when returning a struct in registers, clang will set the 'inreg' flag on the return value, so that behavior is unchanged. This also happens when returning a float _Complex. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199028 91177308-0d34-0410-b5e6-96231b3b80d8
* Add missing mul aliases for armv4 support. Add checks that armv4 canJoerg Sonnenberger2014-01-12
| | | | | | | assemble the various mul instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199026 91177308-0d34-0410-b5e6-96231b3b80d8
* [Sparc] Add missing processor types: v7 and niagaraVenkatraman Govindaraju2014-01-11
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199024 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM IAS: support emitting constant values in target expressionsSaleem Abdulrasool2014-01-11
| | | | | | | | A 32-bit immediate value can be formed from a constant expression and loaded into a register. Add support to emit this into an object file. Because this value is a constant, a relocation must *not* be produced for it. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199023 91177308-0d34-0410-b5e6-96231b3b80d8
* [Sparc] Bundle instruction with delay slow and its filler. Now, we can use ↵Venkatraman Govindaraju2014-01-11
| | | | | | -verify-machineinstrs with SPARC backend. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199014 91177308-0d34-0410-b5e6-96231b3b80d8
* [anyregcc] Fix callee-save mask for anyregccJuergen Ributzka2014-01-11
| | | | | | | Use separate callee-save masks for XMM and YMM registers for anyregcc on X86 and select the proper mask depending on the target cpu we compile for. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198985 91177308-0d34-0410-b5e6-96231b3b80d8
* Must not produce Tag_CPU_arch_profile for pre-ARMv7 cores (e.g. cortex-m0)Artyom Skrobov2014-01-10
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198945 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM: fix regression caused by r198914Saleem Abdulrasool2014-01-10
| | | | | | | | The disassembler would no longer be able to disambiguage between the two variants (explicit immediate #0 vs implicit, omitted #0) for the ldrt, strt, ldrbt, strbt mnemonics as both versions indicated the disassembler routine. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198944 91177308-0d34-0410-b5e6-96231b3b80d8
* Silence unused variable warning for non-asserting builds that was introduced ↵Kristof Beyls2014-01-10
| | | | | | in r198937. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198941 91177308-0d34-0410-b5e6-96231b3b80d8
* Make sure -use-init-array has intended effect on all AArch64 ELF targets, ↵Kristof Beyls2014-01-10
| | | | | | not just linux. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198937 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM IAS: support #:{lower,upper}16: for GNU compatibilitySaleem Abdulrasool2014-01-10
| | | | | | | | The GNU assembler supports prefixing the expression with a '#' to indiciate that the value that is being moved is infact a constant. This improves the compatibility of the integrated assembler's parser for this. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198916 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM IAS: support GNU extension for ldrd, strdSaleem Abdulrasool2014-01-10
| | | | | | | | | The GNU assembler has an extension that allows for the elision of the paired register (dt2) for the LDRD and STRD mnemonics. Add support for this in the assembly parser. Canonicalise the usage during the instruction parsing from the specified version. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198915 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM IAS: support implicit immediate 0s for {LD,ST}R{B,}TSaleem Abdulrasool2014-01-10
| | | | | | | | | | | | | | | | The ARM ARM indicates the mnemonics as follows: ldrbt{<c>}{<q>} <Rt>, [<Rn>], {, #+/-<imm>} ldrt{<c>}{<q>} <Rt>, [<Rn>] {, #+/-<imm>} strbt{<c>}{<q>} <Rt>, [<Rn>] {, #<imm>} strt{<c>}{<q>} <Rt>, [<Rn>] {, #+/-<imm>} This improves the parser to deal with the implicit immediate 0 for the mnemonics as per the specification. Thanks to Joerg Sonnenberger for the tests! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198914 91177308-0d34-0410-b5e6-96231b3b80d8
* [Sparc] Emit retl/ret instead of jmp instruction. It improves the ↵Venkatraman Govindaraju2014-01-10
| | | | | | readability of the assembly generated. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198910 91177308-0d34-0410-b5e6-96231b3b80d8
* [Sparc] Add support for parsing jmpl instruction and make indirect call and ↵Venkatraman Govindaraju2014-01-10
| | | | | | jmp instructions as aliases to jmpl. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198909 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix a bug with the ARM thumb2 CBNZ and CBNZ instructions thatKevin Enderby2014-01-10
| | | | | | | | | | branch to the next instruction. This can not be encoded but can be turned into a NOP. rdar://15062072 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198904 91177308-0d34-0410-b5e6-96231b3b80d8
* [Sparc] Multiclass for loads/stores. No functionality change intended.Venkatraman Govindaraju2014-01-09
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198893 91177308-0d34-0410-b5e6-96231b3b80d8
* Clean up an inconsistency in v7s feature default.Evan Cheng2014-01-09
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198889 91177308-0d34-0410-b5e6-96231b3b80d8
* [SystemZ] Fix RNSBG bug introduced by r197802Richard Sandiford2014-01-09
| | | | | | | | | The zext handling added in r197802 wasn't right for RNSBG. This patch restricts it to ROSBG, RXSBG and RISBG. (The tests for RISBG were added in r197802 since RISBG was the motivating example.) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198862 91177308-0d34-0410-b5e6-96231b3b80d8
* Put the functionality for printing a value to a raw_ostream as anChandler Carruth2014-01-09
| | | | | | | | | | | | operand into the Value interface just like the core print method is. That gives a more conistent organization to the IR printing interfaces -- they are all attached to the IR objects themselves. Also, update all the users. This removes the 'Writer.h' header which contained only a single function declaration. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198836 91177308-0d34-0410-b5e6-96231b3b80d8
* Move declaration of variables down to first use.Matt Arsenault2014-01-08
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198794 91177308-0d34-0410-b5e6-96231b3b80d8
* [AArch64][NEON] Added UXTL and UXTL2 instruction aliasesAna Pazos2014-01-08
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198791 91177308-0d34-0410-b5e6-96231b3b80d8
* [x86] Remove OpSize16 flag from MOV32r0David Woodhouse2014-01-08
| | | | | | It's not a real instruction any more and doesn't need encoding information. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198778 91177308-0d34-0410-b5e6-96231b3b80d8
* [x86] Support R_386_PC8, R_386_PC16 and R_X86_64_PC8David Woodhouse2014-01-08
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198763 91177308-0d34-0410-b5e6-96231b3b80d8
* [x86] Add JMP_2 and other 16-bit PC-relative branch instructionsDavid Woodhouse2014-01-08
| | | | | | | Mark them as requiring 16-bit mode for now, since we don't yet have relaxation support for FK_Data_2. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198762 91177308-0d34-0410-b5e6-96231b3b80d8
* [x86] Do not relax PUSHi16 to PUSHi32 (PR18414)David Woodhouse2014-01-08
| | | | | | | | They do *different* things to %esp, so they are not equivalent. Rename PUSHi8 to PUSH32i8 and add the missing PUSH16i8. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198761 91177308-0d34-0410-b5e6-96231b3b80d8
* [x86] Make AsmParser validate registers for memory operands a bit betterDavid Woodhouse2014-01-08
| | | | | | | | | | | | We can't do a perfect job here. We *have* to allow (%dx) even in 64-bit mode, for example, because it might be used for an unofficial form of the in/out instructions. We actually want to do a better job of validation *later*. Perhaps *instead* of doing it where we are at the moment. But for now, doing what validation we *can* do in the place that the code already has its validation, is an improvement. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198760 91177308-0d34-0410-b5e6-96231b3b80d8
* [x86] Fix MOV8ao8 et al for 16-bit mode, fix up disassembler to understandDavid Woodhouse2014-01-08
| | | | | | | | | | It seems there is no separate instruction class for having AdSize *and* OpSize bits set, which is required in order to disambiguate between all these instructions. So add that to the disassembler. Hm, perhaps we do need an AdSize16 bit after all? git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198759 91177308-0d34-0410-b5e6-96231b3b80d8
* [x86] Use 16-bit addressing where possible in 16-bit modeDavid Woodhouse2014-01-08
| | | | | | | | | Where "where possible" means that it's an immediate value and it's below 0x10000. In fact GAS will either truncate or error with larger values, and will insist on using the addr32 prefix to get 32-bit addressing. So perhaps we should do that, in a later patch. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198758 91177308-0d34-0410-b5e6-96231b3b80d8
* [x86] Fix JCXZ,JECXZ_32 for 16-bit modeDavid Woodhouse2014-01-08
| | | | | | | JCXZ should have the 0x67 prefix only if we're in 32-bit mode, so make that appropriately conditional. And JECXZ needs the prefix instead. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198757 91177308-0d34-0410-b5e6-96231b3b80d8
* [x86] Disambiguate RET[QL] and fix aliases for 16-bit modeDavid Woodhouse2014-01-08
| | | | | | | | | | I couldn't see how to do this sanely without splitting RETQ from RETL. Eric says: "sad about the inability to roundtrip them now, but...". I have no idea what that means, but perhaps it wants preserving in the commit comment. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198756 91177308-0d34-0410-b5e6-96231b3b80d8
* [x86] Disambiguate [LS][IG]DT{32,64}m and add 16-bit versions, fix aliasesDavid Woodhouse2014-01-08
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198755 91177308-0d34-0410-b5e6-96231b3b80d8
* [x86] Add JMP16[rm],CALL16[rm] instructions, and fix up aliasesDavid Woodhouse2014-01-08
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198754 91177308-0d34-0410-b5e6-96231b3b80d8
* [x86] Add PUSHA16,POPA16 instructions, and fix aliases for 16-bit modeDavid Woodhouse2014-01-08
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198753 91177308-0d34-0410-b5e6-96231b3b80d8
* [x86] Add OpSize16 to instructions that need itDavid Woodhouse2014-01-08
| | | | | | | | | This fixes the bulk of 16-bit output, and the corresponding test case x86-16.s now looks mostly like the x86-32.s test case that it was originally based on. A few irrelevant instructions have been dropped, and there are still some corner cases to be fixed in subsequent patches. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198752 91177308-0d34-0410-b5e6-96231b3b80d8
* AVX-512: Added more intrinsics for pmin/pmax, pabs, blend, pmuldq.Elena Demikhovsky2014-01-08
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198745 91177308-0d34-0410-b5e6-96231b3b80d8
* [patch] Adjust behavior of FDE cross-section relocs for targets that don't ↵Iain Sandoe2014-01-08
| | | | | | | | | | | | | | support abs-differences. Modern versions of OSX/Darwin's ld (ld64 > 97.17) have an optimisation present that allows the back end to omit relocations (and replace them with an absolute difference) for FDE some text section refs. This patch allows a backend to opt-in to this behaviour by setting "DwarfFDESymbolsUseAbsDiff". At present, this is only enabled for modern x86 OSX ports. test changes by David Fang. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198744 91177308-0d34-0410-b5e6-96231b3b80d8
* [AArch64 NEON] Fix generating incorrect value type of NEON_VDUPLANEKevin Qin2014-01-08
| | | | | | | when lower build_vector if result value type mismatch with operand value type. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198743 91177308-0d34-0410-b5e6-96231b3b80d8
* [SparcV9] Rename operands in some sparc64 instructions so that TableGen can ↵Venkatraman Govindaraju2014-01-08
| | | | | | encode them correctly. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198740 91177308-0d34-0410-b5e6-96231b3b80d8
* [Sparc] Correct the mask for fixup_sparc_br19.Venkatraman Govindaraju2014-01-08
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198739 91177308-0d34-0410-b5e6-96231b3b80d8
* [Sparc] Add support for parsing branch instructions and conditional moves.Venkatraman Govindaraju2014-01-08
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198738 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM IAS: properly handle expression operandsSaleem Abdulrasool2014-01-08
| | | | | | | Operands which involved label arithemetic would previously fail to parse. This corrects that by adding the additional case for the shift operand validation. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198735 91177308-0d34-0410-b5e6-96231b3b80d8
* [x86] Kill gratuitous X86_{32,64}TargetMachine subclasses, use X86TargetMachineDavid Woodhouse2014-01-08
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198720 91177308-0d34-0410-b5e6-96231b3b80d8
* Move the llvm mangler to lib/IR.Rafael Espindola2014-01-07
| | | | | | This makes it available to tools that don't link with target (like llvm-ar). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198708 91177308-0d34-0410-b5e6-96231b3b80d8
* Don't assert with private type info variables.Rafael Espindola2014-01-07
| | | | | | | With the gnu objc runtime private strings are used. Since we only need to produce a unique label, the fix is to just drop the asserts. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198701 91177308-0d34-0410-b5e6-96231b3b80d8
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