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* Tidy up several unbeseeming casts from pointer to intptr_t.Dan Gohman2008-09-04
* Fix the ordering of operands to the store (inverted relative to LLVM IR), and...Owen Anderson2008-09-04
* Clean up uses of TargetLowering::getTargetMachine.Dan Gohman2008-09-04
* Add a first attempt at implementing stores for X86 fast isel using target hooks.Owen Anderson2008-09-04
* Load from GV stub should be locally CSE'd.Evan Cheng2008-09-04
* Remove code that pad number of bytes to pop for X86_FastCall CC. The code doe...Evan Cheng2008-09-04
* Add intrinsics for log, log2, log10, exp, exp2.Dale Johannesen2008-09-04
* Create HandlePHINodesInSuccessorBlocksFast, a version ofDan Gohman2008-09-03
* Add X86 target hook to implement load (even from GlobalAddress).Evan Cheng2008-09-03
* Fix capitalization in #include of FastISel.h. This unbreaks the build on cas...Ted Kremenek2008-09-03
* Unbreak fast isel.Evan Cheng2008-09-03
* Let tblgen only generate fastisel routines, not the class definition. This ma...Evan Cheng2008-09-03
* Fix some bugs in the code sequences for atomics.Dale Johannesen2008-09-02
* Add Mac OS X compatible JIT callback routine.Evan Cheng2008-09-02
* Revamp ARM JIT.Evan Cheng2008-09-02
* Change getBinaryCodeForInstr prototype. First operand MachineInstr& should be...Evan Cheng2008-09-02
* Control flow instruction encodings.Evan Cheng2008-09-01
* ldm / stm instruction encodings.Evan Cheng2008-09-01
* AXI2 and AXI3 instruction encodings.Evan Cheng2008-09-01
* Reorganize instruction formats again; AXI1 encoding.Evan Cheng2008-09-01
* addrmode3 instruction encodings.Evan Cheng2008-09-01
* Reorganize some instruction format definitions. No functionality change.Evan Cheng2008-09-01
* Rest of addrmode2 instruction encodings.Evan Cheng2008-09-01
* Addr2 word / byte load encodings.Evan Cheng2008-08-31
* Addr1 instructions opcodes are encoded in bits 21-24; encode S bit.Evan Cheng2008-08-31
* fix a bunch of 80-col violationsGabor Greif2008-08-31
* Revert the "XFAIL" for the rotate_ops.ll testcase. Instead, mark ISD::ROTRBill Wendling2008-08-31
* Expand for ROTR with MVT::i64.Bill Wendling2008-08-31
* fix some 80-col violationsGabor Greif2008-08-30
* For now, can't mark XOR64rr isAsCheapAsAMove. It's technically correct. But v...Evan Cheng2008-08-30
* Transform (x << (y&31)) -> (x << y). This takes advantage of the fact x86 shi...Evan Cheng2008-08-30
* Add ppc partial-word ATOMIC_CMP_SWAP.Dale Johannesen2008-08-30
* Swap fp comparison operands and change predicate to allow load folding (safel...Evan Cheng2008-08-29
* Use static_cast instead of C style cast.Evan Cheng2008-08-29
* Backing out 55521. Not safe.Evan Cheng2008-08-29
* Add partial word version of ATOMIC_SWAP.Dale Johannesen2008-08-29
* Add initial support for fast isel of instructions that have inputs pinned to ...Owen Anderson2008-08-29
* TableGen'ing instruction encodings.Evan Cheng2008-08-29
* addrmode1 (data processing) instruction encoding: bits 5-6 are 0, bits 7-10 e...Evan Cheng2008-08-29
* MVN is addrmode1.Evan Cheng2008-08-29
* More refactoring.Evan Cheng2008-08-29
* Swap fp comparison operands and change predicate to allow load folding.Evan Cheng2008-08-28
* Refactor ARM instruction format definitions into a separate file. No function...Evan Cheng2008-08-28
* Add a target callback for FastISel.Dan Gohman2008-08-28
* remove tabs, fix > 80 colsGabor Greif2008-08-28
* erect abstraction boundaries for accessing SDValue members, rename Val -> Nod...Gabor Greif2008-08-28
* In lowering SELECT_CC, removed cases where we can't flip the true and false w...Mon P Wang2008-08-28
* Use resize instead of reserve. Reserve doesn't change size().Rafael Espindola2008-08-28
* Implement partial-word binary atomics on ppc.Dale Johannesen2008-08-28
* FsFLD0S{S|D} and V_SETALLONES are as cheap as moves.Evan Cheng2008-08-28
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