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* [NVPTX] Add support for vectorized function return valuesJustin Holewinski2013-06-28
* [NVPTX] Clean up handling of formal arguments and enable generation of vector...Justin Holewinski2013-06-28
* [NVPTX] Add infrastructure for vector loads/stores of parametersJustin Holewinski2013-06-28
* Bug 13662: Enable GPRPair for all i64 operands of inline asm on ARMWeiming Zhao2013-06-28
* R600: Add local memory support via LDSTom Stellard2013-06-28
* R600: Add support for GROUP_BARRIER instructionTom Stellard2013-06-28
* R600: Add ALUInst bit to tablegen definitions v2Tom Stellard2013-06-28
* ARM: ensure fixed-point conversions have sane typesTim Northover2013-06-28
* ARM: Fix pseudo-instructions for SRS (Store Return State).Tilmann Scheller2013-06-28
* Debug Info: clean up usage of Verify.Manman Ren2013-06-28
* Integrate Assembler: Support X86_64_DTPOFF64 relocationsDavid Blaikie2013-06-28
* Get rid of the unused class member.Nadav Rotem2013-06-27
* CostModel: improve the cost model for load/store of non power-of-two types su...Nadav Rotem2013-06-27
* Add a Subtarget feature 'v8fp' to the ARM backend.Joey Gouly2013-06-27
* Don't cast away constness.Benjamin Kramer2013-06-27
* [SystemZ] Allow LA and LARL to be rematerializedRichard Sandiford2013-06-27
* [SystemZ] Allow immediate moves to be rematerializedRichard Sandiford2013-06-27
* [SystemZ] Add conditional store patternsRichard Sandiford2013-06-27
* Revert "Debug Info: clean up usage of Verify." as it's breaking bots.Eric Christopher2013-06-26
* Clarify and doxygen-ify commentsStephen Lin2013-06-26
* [Mips Disassembler] Have the DecodeCCRRegisterClass function use the getRegChad Rosier2013-06-26
* ARM: Proactively ensure that the LowerCallResult hack for 'this'-returns is n...Stephen Lin2013-06-26
* Debug Info: clean up usage of Verify.Manman Ren2013-06-26
* Minor formatting fix to ARMBaseRegisterInfo::getCalleeSavedRegsStephen Lin2013-06-26
* [mips] Do not emit ".option pic0" if target is mips64.Akira Hatanaka2013-06-26
* [mips] Improve code generation for constant multiplication using shifts, adds...Akira Hatanaka2013-06-26
* Add a subtarget feature 'v8' to the ARM backend.Joey Gouly2013-06-26
* ARM: fix more cases where predication may or may not be allowedTim Northover2013-06-26
* ARM: allow predicated barriers in Thumb modeTim Northover2013-06-26
* Remove the 'generic' CPU from the ARM eabi attributes printer.Joey Gouly2013-06-26
* [PowerPC] Accept 17-bit signed immediates for addisUlrich Weigand2013-06-26
* [PowerPC] Support symbolic u16imm operandsUlrich Weigand2013-06-26
* ARM: operands should be explicit when disassembledAmaury de la Vieuville2013-06-26
* [Sparc]: Add memory operands for the frame references in the storeRegToStackSlotVenkatraman Govindaraju2013-06-26
* Optimized integer vector multiplication operation by replacing it with shift/...Elena Demikhovsky2013-06-26
* R600: Use new getNamedOperandIdx function generated by TableGenTom Stellard2013-06-25
* X86 cost model: Vectorizing integer division is a bad ideaArnold Schwaighofer2013-06-25
* [PowerPC] Support @got modifierUlrich Weigand2013-06-25
* R600: Consolidate expansion of v2i32/v4i32 ops for EG/SIAaron Watry2013-06-25
* R600/SI: Expand xor v2i32/v4i32Aaron Watry2013-06-25
* R600/SI: Expand urem of v2i32/v4i32 for SIAaron Watry2013-06-25
* R600/SI: Expand udiv v[24]i32 for SI and v2i32 for EGAaron Watry2013-06-25
* R600/SI: Expand ashr of v2i32/v4i32 for SIAaron Watry2013-06-25
* R600/SI: Expand srl of v2i32/v4i32 for SIAaron Watry2013-06-25
* R600/SI: Expand shl of v2i32/v4i32 for SIAaron Watry2013-06-25
* R600/SI: Expand or of v2i32/v4i32 for SIAaron Watry2013-06-25
* R600/SI: Expand mul of v2i32/v4i32 for SIAaron Watry2013-06-25
* R600/SI: Expand and of v2i32/v4i32 for SIAaron Watry2013-06-25
* [PowerPC] Add extended rotate/shift mnemonicsUlrich Weigand2013-06-25
* [PowerPC] Add rldcr/rldic instructionsUlrich Weigand2013-06-25
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