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* ARM: Remove a (false) dependency on the memoryoperand's value as we do not useQuentin Colombet2013-06-20
* [PowerPC] Clean up VK_PPC_TOC... namesUlrich Weigand2013-06-20
* Update the X86 disassembler to use xacquire and xrelease when appropriate.Kevin Enderby2013-06-20
* [PowerPC] Minor cleanup in PPCELFObjectWriter::getRelocTypeInnerUlrich Weigand2013-06-20
* R600/SI: Expand sub for v2i32 and v4i32 for SITom Stellard2013-06-20
* R600/SI: Expand add for v2i32 and v4i32Tom Stellard2013-06-20
* R600: Expand v2i32 load/store instead of custom loweringTom Stellard2013-06-20
* This reverts r155000.Joey Gouly2013-06-20
* [PowerPC] Remove unused parameterUlrich Weigand2013-06-20
* [PowerPC] Add missing build dependencyUlrich Weigand2013-06-20
* [PowerPC] Optimize @ha/@l constructsUlrich Weigand2013-06-20
* [PowerPC] Support compare mnemonics with implied CR0Ulrich Weigand2013-06-20
* Optimize register parsing for MipsAsmParser. Allow symbolic aliases for FPU r...Vladimir Medic2013-06-20
* Don't pass in the TargetInstrInfo into the register info object. It doesn't u...Bill Wendling2013-06-19
* DebugInfo: PR14763/r183329 correct the location of indirect parametersDavid Blaikie2013-06-19
* Access the TargetLoweringInfo from the TargetMachine object instead of cachin...Bill Wendling2013-06-19
* Access the TargetLoweringInfo from the TargetMachine object instead of cachin...Bill Wendling2013-06-19
* Access the TargetLoweringInfo from the TargetMachine object instead of cachin...Bill Wendling2013-06-19
* Move StructurizeCFG out of R600 to generic Transforms.Matt Arsenault2013-06-19
* The RenderMethod field in RegisterOperand class sets the name of the method o...Vladimir Medic2013-06-19
* Use GetUnderlyingObject instead of custom functionMatt Arsenault2013-06-18
* ARM: Add optional datatype suffix to NEON mvn asm syntax.Jim Grosbach2013-06-18
* [ARMTargetLowering] ARMISD::{SUB,ADD}{C,E} second result is a boolean implyin...Michael Gottesman2013-06-18
* Converted an overly aggressive assert to a conditional check in AddCombineTo6...Michael Gottesman2013-06-18
* Fix 80 col violation.Nadav Rotem2013-06-18
* Change the arm assembler to support this from the v7c spec:Kevin Enderby2013-06-18
* Mips ELF: Mark object file as ABI compliant Jack Carter2013-06-18
* Reduce indentation.David Blaikie2013-06-18
* Add support for encoding the HLE XACQUIRE and XRELEASE prefixes.Stefanus Du Toit2013-06-18
* ARM: fix literal load with positive offset encodingAmaury de la Vieuville2013-06-18
* ARM: add operands pre-writeback variants when neededAmaury de la Vieuville2013-06-18
* ARM: fix thumb literal loads decodingAmaury de la Vieuville2013-06-18
* ARM: thumb stores cannot use PC as dest registerAmaury de la Vieuville2013-06-18
* Use pointers to the MCAsmInfo and MCRegInfo.Bill Wendling2013-06-18
* Remove dead prototype.Bill Wendling2013-06-18
* R600: PV stores Reg id, not indexVincent Lejeune2013-06-17
* R600: Properly set COUNT_3 bit in TEX clause initiating inst for pre EG gen.Vincent Lejeune2013-06-17
* DebugInfo: remove target-specific Frame Index handling for DBG_VALUE MachineI...David Blaikie2013-06-16
* Debug Info: Simplify Frame Index handling in DBG_VALUE Machine InstructionsDavid Blaikie2013-06-16
* Support BufferSize on ProcResGroup for unified MOp schedulers.Andrew Trick2013-06-15
* Update machine models. Specify buffer sizes for OOO processors.Andrew Trick2013-06-15
* Machine Model: Add MicroOpBufferSize and resource BufferSize.Andrew Trick2013-06-15
* R600: Add SI load support for v[24]i32 and store for v2i32Tom Stellard2013-06-15
* R600: Use correct encoding for Vertex Fetch instructions on CaymanTom Stellard2013-06-14
* R600: Use EXPORT_RAT_INST_STORE_DWORD for stores on CaymanTom Stellard2013-06-14
* R600: Factor the instruction encoding out the RAT_WRITE_CACHELESS_eg classTom Stellard2013-06-14
* R600: Move instruction encoding definitions into a separate .td fileTom Stellard2013-06-14
* ARM: fix thumb coprocessor instruction with pre-writeback disassemblyAmaury de la Vieuville2013-06-14
* X86: cvtpi2ps is just an SSE instruction with MMX operands. It has no AVX equ...Benjamin Kramer2013-06-14
* Enable FastISel on ARM for Linux and NaCl, not MCJITJF Bastien2013-06-14
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