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* [FastISel][X86] Fix typos.Juergen Ributzka2014-06-27
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211911 91177308-0d34-0410-b5e6-96231b3b80d8
* R600: Don't crash on unhandled instruction in promote allocaMatt Arsenault2014-06-27
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211906 91177308-0d34-0410-b5e6-96231b3b80d8
* Clean up unused variable warning in release build.Alexander Kornienko2014-06-27
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211902 91177308-0d34-0410-b5e6-96231b3b80d8
* [PowerPC] Constrain base register in PPCRegisterInfo::resolveFrameIndexUlrich Weigand2014-06-27
| | | | | | | | | | | | | | | | | | | | | | | | I've run into a bug where current LLVM at -O0 (with fast-isel) generated invalid code like: ld 0, 20936(1) # 8-byte Folded Reload stw 12, 10348(0) stw 12, 10344(0) The underlying vreg had been introduced as base register by the Local Stack Slot Allocation pass. That register was constrained to G8RC by PPCRegisterInfo::materializeFrameBaseRegister to match the ADDI instruction used to set it, but it was *not* constrained to G8RC_NOX0 to fit the *use* of the register in an address. That should have happened in PPCRegisterInfo::resolveFrameIndex. This patch adds an appropriate constrainRegClass call. Reviewed by Hal Finkel. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211897 91177308-0d34-0410-b5e6-96231b3b80d8
* [x86] Clean up some unused variables, especially in release builds.Chandler Carruth2014-06-27
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211894 91177308-0d34-0410-b5e6-96231b3b80d8
* [x86] Teach the target combine step to aggressively fold pshufd insturcions.Chandler Carruth2014-06-27
| | | | | | | | | | | | | Summary: This allows it to fold pshufd instructions across intervening half-shuffles and other noise. This pattern actually shows up in the generic lowering tests, but I've also added direct tests using intrinsics to make sure that the specific desired functionality is working even if the lowering stuff changes in the future. Differential Revision: http://reviews.llvm.org/D4292 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211892 91177308-0d34-0410-b5e6-96231b3b80d8
* [x86] Teach the target-specific combining how to aggressively foldChandler Carruth2014-06-27
| | | | | | | | | | | | | | | | | | half-shuffles, even looking through intervening instructions in a chain. Summary: This doesn't happen to show up with any test cases I've found for the current shuffle lowering, but previous attempts would benefit from this and it seems generally useful. I've tested it directly using intrinsics, which also shows that it will work with hand vectorized code as well. Note that even though pshufd isn't directly used in these tests, it gets exercised because we combine some of the half shuffles into a pshufd first, and then merge them. Differential Revision: http://reviews.llvm.org/D4291 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211890 91177308-0d34-0410-b5e6-96231b3b80d8
* [x86] Teach the X86 backend to DAG-combine SSE2 shuffles that areChandler Carruth2014-06-27
| | | | | | | | | | | | | | | | | trivially redundant. This fixes several cases in the new vector shuffle lowering algorithm which would generate redundant shuffle instructions for the sake of simplicity. I'm also deleting a testcase which was somewhat ridiculous. It was checking for a bug in 2007 about incorrectly transforming shuffles by looking for the string "-86" in the output of a pretty substantial function. This test case doesn't seem to have any value at this point. Differential Revision: http://reviews.llvm.org/D4240 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211889 91177308-0d34-0410-b5e6-96231b3b80d8
* [x86] Begin a significant overhaul of how vector lowering is done in theChandler Carruth2014-06-27
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | x86 backend. This sketches out a new code path for vector lowering, hidden behind an off-by-default flag while it is under development. The fundamental idea behind the new code path is to aggressively break down the problem space in ways that ease selecting the odd set of instructions available on x86, and carefully avoid scalarizing code even when forced to use older ISAs. Notably, this starts off restricting itself to SSE2 and implements the complete vector shuffle and blend space for 128-bit vectors in SSE2 without scalarizing. The plan is to layer on top of this ISA extensions where we can bail out of the complex SSE2 lowering and opt for a cheaper, specialized instruction (or set of instructions). It also needs to be generalized to AVX and AVX512 vector widths. Currently, this does a decent but not perfect job for SSE2. There are some specific shortcomings that I plan to address: - We need a peephole combine to fold together shuffles where possible. There are cases where a previous shuffle could be modified slightly to arrange for elements to be in the correct position and a later shuffle eliminated. Doing this eagerly added quite a bit of complexity, and so my plan is to combine away these redundancies afterward. - There are a lot more clever ways to use unpck and pack that need to be added. This is essential for real world shuffles as it turns out... Once SSE2 is polished a bit I should be able to get interesting numbers on performance improvements on benchmarks conducive to vectorization. All of this will be off by default until it is functionally equivalent of course. Differential Revision: http://reviews.llvm.org/D4225 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211888 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove the caching of the target machine from SystemZTargetLowering.Eric Christopher2014-06-27
| | | | | | Update all callers and uses accordingly. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211880 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove target machine caching from SystemZInstrInfo andEric Christopher2014-06-27
| | | | | | | | SystemZRegisterInfo and replace it with the subtarget as that's all they needed in the first place. Update all uses and calls accordingly. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211877 91177308-0d34-0410-b5e6-96231b3b80d8
* Have SystemZSelectionDAGInfo constructor take a DataLayout ratherEric Christopher2014-06-27
| | | | | | | than a target machine since it doesn't need anything past the DataLayout. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211870 91177308-0d34-0410-b5e6-96231b3b80d8
* Rename getX86ConditonCode -> getX86ConditionCodeCraig Topper2014-06-27
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211869 91177308-0d34-0410-b5e6-96231b3b80d8
* Have MipsSelectionDAGInfo constructor take a DataLayout ratherEric Christopher2014-06-27
| | | | | | | than a target machine since it doesn't need anything past the DataLayout. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211863 91177308-0d34-0410-b5e6-96231b3b80d8
* Move NVPTX subtarget dependent variables from the target machineEric Christopher2014-06-27
| | | | | | to the subtarget. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211860 91177308-0d34-0410-b5e6-96231b3b80d8
* Use the target lowering we can get off of the DAG rather than offEric Christopher2014-06-27
| | | | | | of the cached target machine. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211858 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix missing newline and simplify debug printing.Matt Arsenault2014-06-27
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211850 91177308-0d34-0410-b5e6-96231b3b80d8
* R600: Move load/store ReplaceNodeResults to common code.Matt Arsenault2014-06-27
| | | | | | Future patches will want to custom lower loads on SI. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211848 91177308-0d34-0410-b5e6-96231b3b80d8
* Move the constructor for NVPTXFrameLowering into the implementationEric Christopher2014-06-27
| | | | | | file in preparation for the subtarget move. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211847 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove unnecessary caching of the TargetMachine on NVPTXFrameLowering.Eric Christopher2014-06-27
| | | | | | Adjust the constructor accordingly. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211846 91177308-0d34-0410-b5e6-96231b3b80d8
* Rework the logic for setting the TargetName. This appears toEric Christopher2014-06-27
| | | | | | be shorter and identical in goal. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211845 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove caching of the target machine in NVPTXInstrInfo andEric Christopher2014-06-27
| | | | | | update constructor accordingly. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211840 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove comment that duplicated information in the constructorEric Christopher2014-06-27
| | | | | | that it's after. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211839 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove commented out code.Eric Christopher2014-06-27
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211838 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove extraneous parens and extraneous const cast (and fix theEric Christopher2014-06-27
| | | | | | prototype for the function to patch what we were returning). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211837 91177308-0d34-0410-b5e6-96231b3b80d8
* Move the subtarget dependent features from the target machine toEric Christopher2014-06-27
| | | | | | the subtarget for the MSP430 target. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211836 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove uses and caches of the target machine and subtarget fromEric Christopher2014-06-27
| | | | | | | | both MSP430InstrInfo and MSP430RegisterInfo. Remove unused member variable StackAlign from MSP430RegisterInfo. Update constructors accordingly. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211835 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove caching of an unused subtarget from MSP430FrameLowering.Eric Christopher2014-06-27
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211830 91177308-0d34-0410-b5e6-96231b3b80d8
* [X86] AVX512: Add vbroadcasti*Adam Nemet2014-06-27
| | | | | | | | | For now I used a separate template for these sub-vector/tuple broadcasts rather than sharing the mem variants with avx512_int_broadcast_rm. <rdar://problem/17402869> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211828 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove unnecessary caching of variables by MSP430TargetLowering andEric Christopher2014-06-27
| | | | | | | make the constructor more general since it only needs a target machine. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211827 91177308-0d34-0410-b5e6-96231b3b80d8
* Have MSP430SelectionDAGInfo constructor take a DataLayout ratherEric Christopher2014-06-27
| | | | | | | than a target machine since it doesn't need anything past the DataLayout. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211826 91177308-0d34-0410-b5e6-96231b3b80d8
* Move all of the hexagon subtarget dependent variables from the targetEric Christopher2014-06-27
| | | | | | machine to the subtarget. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211824 91177308-0d34-0410-b5e6-96231b3b80d8
* Have HexagonSelectionDAGInfo take a DataLayout rather than aEric Christopher2014-06-27
| | | | | | target machine since that's all it needs. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211822 91177308-0d34-0410-b5e6-96231b3b80d8
* Make HexagonISelLowering not dependent upon a HexagonTargetMachine,Eric Christopher2014-06-27
| | | | | | but a normal TargetMachine and remove a few cached uses. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211821 91177308-0d34-0410-b5e6-96231b3b80d8
* Reduce indentation.Eric Christopher2014-06-27
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211820 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove unnecessary caching of the subtarget for HexagonFrameLowering and ↵Eric Christopher2014-06-27
| | | | | | remove the unused constructor argument. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211819 91177308-0d34-0410-b5e6-96231b3b80d8
* InstrItineraryData is already on the subtarget, no reason toEric Christopher2014-06-27
| | | | | | cache it on the target as well. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211818 91177308-0d34-0410-b5e6-96231b3b80d8
* Revert "Introduce a string_ostream string builder facilty"Alp Toker2014-06-26
| | | | | | Temporarily back out commits r211749, r211752 and r211754. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211814 91177308-0d34-0410-b5e6-96231b3b80d8
* Move the various Subtarget dependent members down to the subtargetEric Christopher2014-06-26
| | | | | | | | for the Sparc port. Use the same initializeSubtargetDependencies function to handle initialization similar to the other ports to handle dependencies. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211811 91177308-0d34-0410-b5e6-96231b3b80d8
* Have SparcSelectionDAGInfo take a DataLayout to initialize sinceEric Christopher2014-06-26
| | | | | | that's all it needs. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211810 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove the storage and use of the subtarget out of the sparc frameEric Christopher2014-06-26
| | | | | | lowering code. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211809 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove extraneous includes from the target machines.Eric Christopher2014-06-26
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211800 91177308-0d34-0410-b5e6-96231b3b80d8
* Move all of the ARM subtarget features down onto the subtargetEric Christopher2014-06-26
| | | | | | rather than the target machine. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211799 91177308-0d34-0410-b5e6-96231b3b80d8
* Move the frame lowering constructors out of line to avoid circularEric Christopher2014-06-26
| | | | | | includes. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211798 91177308-0d34-0410-b5e6-96231b3b80d8
* R600/SI: Add FP mode bits to binary.Matt Arsenault2014-06-26
| | | | | | | | The default rounding mode to initialize the mode register needs to be reported to the runtime. Fill in other bits a kernel may be interested in setting for future use. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211791 91177308-0d34-0410-b5e6-96231b3b80d8
* Silencing a warning about isZExtFree hiding an inherited virtual function. ↵Aaron Ballman2014-06-26
| | | | | | No functional change intended. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211783 91177308-0d34-0410-b5e6-96231b3b80d8
* Silence a warning due to a comparison between signed and unsigned.Andrea Di Biagio2014-06-26
| | | | | | | | No functional change intended. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211782 91177308-0d34-0410-b5e6-96231b3b80d8
* add ppc64/pwr8 as targetWill Schmidt2014-06-26
| | | | | | | | | includes handling DIR_PWR8 where appropriate The P7Model Itinerary is currently tied in for use under the P8Model, and will be updated later. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211779 91177308-0d34-0410-b5e6-96231b3b80d8
* Added parsing co-processor names starting with "cr"Renato Golin2014-06-26
| | | | | | | | | | Additional compliant GAS names for coprocessor register name are enabled for all instruction with parameter MCK_CoprocReg: LDC,LDC2,STC,STC2,CDP,CDP2,MCR,MCR2,MCRR,MCRR2,MRC,MRC2,MRRC,MRRC2 Patch by Andrey Kuharev. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211776 91177308-0d34-0410-b5e6-96231b3b80d8
* [X86] Improve the selection of SSE3/AVX addsub instructions. Andrea Di Biagio2014-06-26
| | | | | | | | | | | | | | | | | | | | | | | | | | | This patch teaches the backend how to canonicalize a shuffle vectors according to the rule: - (shuffle (FADD A, B), (FSUB A, B), Mask) -> (shuffle (FSUB A, -B), (FADD A, -B), Mask) Where 'Mask' is: <0,5,2,7> ;; for v4f32 and v4f64 shuffles. <0,3> ;; for v2f64 shuffles. <0,9,2,11,4,13,6,15> ;; for v8f32 shuffles. In general, ISel only knows how to pattern-match a canonical 'fadd + fsub + blendi' dag node sequence into an ADDSUB instruction. This new rule allows to convert a non-canonical dag sequence into a canonical one that will be matched by a single ADDSUB at ISel stage. The idea of converting a non-canonical ADDSUB into a canonical one by swapping the first two operands of the shuffle, and then negating the second operand of the FADD and FSUB, was originally proposed by Hal Finkel. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211771 91177308-0d34-0410-b5e6-96231b3b80d8
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