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* C++ has a bool type! (And C's had one too, for 15 years...)Richard Smith2014-04-20
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206723 91177308-0d34-0410-b5e6-96231b3b80d8
* More C++ification.Richard Smith2014-04-20
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206722 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove some more C junk from these files.Richard Smith2014-04-20
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206721 91177308-0d34-0410-b5e6-96231b3b80d8
* Don't provide two different definitions of ModRMDecision, OpcodeDecision, ↵Richard Smith2014-04-20
| | | | | | and ContextDecision in different source files (depending on #define magic). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206720 91177308-0d34-0410-b5e6-96231b3b80d8
* Don't define llvm::X86Disassembler::InstructionSpecifier in different ways inRichard Smith2014-04-20
| | | | | | | different source files. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206719 91177308-0d34-0410-b5e6-96231b3b80d8
* Maybe if I touch this file the buildbots will actually rerun configure like ↵Richard Smith2014-04-20
| | | | | | they need to... git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206718 91177308-0d34-0410-b5e6-96231b3b80d8
* What year is it! This file has no reason to be written in C, and has doubly noRichard Smith2014-04-20
| | | | | | | | | | | reason to expose a global symbol 'decodeInstruction' nor to pollute the global scope with a bunch of external linkage entities (some of which conflict with others elsewhere in LLVM). This is just the initial transition to C++; more cleanups to follow. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206717 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove some empty statementsAlp Toker2014-04-19
| | | | | | Cleanup only. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206710 91177308-0d34-0410-b5e6-96231b3b80d8
* Patch by Vadim ChugunovYaron Keren2014-04-19
| | | | | | | | | | | | | Win64 stack unwinder gets confused when execution flow "falls through" after a call to 'noreturn' function. This fixes the "missing epilogue" problem by emitting a trap instruction for IR 'unreachable' on x86_x64-pc-windows. A secondary use for it would be for anyone wanting to make double-sure that 'noreturn' functions, indeed, do not return. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206684 91177308-0d34-0410-b5e6-96231b3b80d8
* Change the ARM assembler to require a :lower16: or :upper16 on non-constantKevin Enderby2014-04-18
| | | | | | | | | | | | | | | | | | | | | | | expressions for mov instructions instead of silently truncating by default. For the ARM assembler, we want to avoid misleadingly allowing something like "mov r0, <symbol>" especially when we turn it into a movw and the expression <symbol> does not have a :lower16: or :upper16" as part of the expression. We don't want the behavior of silently truncating, which can be unexpected and lead to bugs that are difficult to find since this is an easy mistake to make. This does change the previous behavior of llvm but actually matches an older gnu assembler that would not allow this but print less useful errors of like “invalid constant (0x927c0) after fixup” and “unsupported relocation on symbol foo”. The error for llvm is "immediate expression for mov requires :lower16: or :upper16" with correct location information on the operand as shown in the added test cases. rdar://12342160 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206669 91177308-0d34-0410-b5e6-96231b3b80d8
* [ARM64] Ports the Cortex-A53 Machine Model description from AArch64.Chad Rosier2014-04-18
| | | | | | | | | | | | | Summary: This port includes the rudimentary latencies that were provided for the Cortex-A53 Machine Model in the AArch64 backend. It also changes the SchedAlias for COPY in the Cyclone model to an explicit WriteRes mapping to avoid conflicts in other subtargets. Differential Revision: http://reviews.llvm.org/D3427 Patch by Dave Estes <cestes@codeaurora.org>! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206652 91177308-0d34-0410-b5e6-96231b3b80d8
* [X86] Improve buildFromShuffleMostly for AVXAdam Nemet2014-04-18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | For a 256-bit BUILD_VECTOR consisting mostly of shuffles of 256-bit vectors, both the BUILD_VECTOR and its operands may need to be legalized in multiple steps. Consider: (v8f32 (BUILD_VECTOR (extract_vector_elt (v8f32 %vreg0,) Constant<1>), (extract_vector_elt %vreg0, Constant<2>), (extract_vector_elt %vreg0, Constant<3>), (extract_vector_elt %vreg0, Constant<4>), (extract_vector_elt %vreg0, Constant<5>), (extract_vector_elt %vreg0, Constant<6>), (extract_vector_elt %vreg0, Constant<7>), %vreg1)) a. We can't build a 256-bit vector efficiently so, we need to split it into two 128-bit vecs and combine them with VINSERTX128. b. Operands like (extract_vector_elt (v8f32 %vreg0), Constant<7>) needs to be split into a VEXTRACTX128 and a further extract_vector_elt from the resulting 128-bit vector. c. The extract_vector_elt from b. is lowered into a shuffle to the first element and a movss. Depending on the order in which we legalize the BUILD_VECTOR and its operands[1], buildFromShuffleMostly may be faced with: (v4f32 (BUILD_VECTOR (extract_vector_elt (vector_shuffle<1,u,u,u> (extract_subvector %vreg0, Constant<4>), undef), Constant<0>), (extract_vector_elt (vector_shuffle<2,u,u,u> (extract_subvector %vreg0, Constant<4>), undef), Constant<0>), (extract_vector_elt (vector_shuffle<3,u,u,u> (extract_subvector %vreg0, Constant<4>), undef), Constant<0>), %vreg1)) In order to figure out the underlying vector and their identity we need to see through the shuffles. [1] Note that the order in which operations and their operands are legalized is only guaranteed in the first iteration of LegalizeDAG. Fixes <rdar://problem/16296956> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206634 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM64: disable generation of .loh directives outside MachO.Tim Northover2014-04-18
| | | | | | Part of PR19455. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206611 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM64: don't emit .subsections_via_symbols on ELF.Tim Northover2014-04-18
| | | | | | Part of PR19455. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206610 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM64: add extra NEG pattern.Tim Northover2014-04-18
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206609 91177308-0d34-0410-b5e6-96231b3b80d8
* AArch64/ARM64: add non-scalar lowering for more FCVT operations.Tim Northover2014-04-18
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206591 91177308-0d34-0410-b5e6-96231b3b80d8
* AArch64/ARM64: improve spotting of EXT instructions from VECTOR_SHUFFLE.Tim Northover2014-04-18
| | | | | | | We couldn't cope if the first mask element was UNDEF before, which isn't ideal. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206588 91177308-0d34-0410-b5e6-96231b3b80d8
* X86: Pattern match scalar loads + vcvtph2ps into just vcvtph2ps.Benjamin Kramer2014-04-18
| | | | | | | vcvtph2ps only reads the lower 64 bits of the address passed to the intrinsic. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206579 91177308-0d34-0410-b5e6-96231b3b80d8
* AArch64/ARM64: spot a greater variety of concat_vector operations.Tim Northover2014-04-18
| | | | | | | | | | Code mostly copied from AArch64, just tidied up a trifle and plumbed into the ARM64 way of doing things. This also enables the AArch64 tests which inspired the previous untested commits. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206574 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM64: implement cunning optimisation from AArch64Tim Northover2014-04-18
| | | | | | | | A vector extract followed by a dup can become a single instruction even if the types don't match. AArch64 handled this in ISelLowering, but a few reasonably simple patterns can take care of it in TableGen, so that's where I've put it. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206573 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM64: spot a vector_shuffle that maps to INS and expand.Tim Northover2014-04-18
| | | | | | | Tests will be coming very shortly when all the optimisations needed to support AArch64's neon-copy.ll file are committed. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206572 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM64: nick some AArch64 patterns for extract/insert -> INS.Tim Northover2014-04-18
| | | | | | | Tests will be committed shortly when all optimisations needed to support AArch64's neon-copy.ll file are supported. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206571 91177308-0d34-0410-b5e6-96231b3b80d8
* AArch64/ARM64: emit all vector FP comparisons as such.Tim Northover2014-04-18
| | | | | | | | | | | | ARM64 was scalarizing some vector comparisons which don't quite map to AArch64's compare and mask instructions. AArch64's approach of sacrificing a little efficiency to emulate them with the limited set available was better, so I ported it across. More "inspired by" than copy/paste since the backend's internal expectations were a bit different, but the tests were invaluable. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206570 91177308-0d34-0410-b5e6-96231b3b80d8
* AArch64/ARM64: port BSL logic from AArch64 & enable test.Tim Northover2014-04-18
| | | | | | | | | | | I enhanced it a little in the process. The decision shouldn't really be beased on whether a BUILD_VECTOR is a splat: any set of constants will do the job provided they're related in the correct way. Also, the BUILD_VECTOR could be any operand of the incoming AND nodes, so it's best to check for all 4 possibilities rather than assuming it'll be the RHS. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206569 91177308-0d34-0410-b5e6-96231b3b80d8
* AArch64/ARM64: copy byval implementation from AArch64.Tim Northover2014-04-18
| | | | | | | | It's not actually used to handle C or C++ ABI rules on ARM64, but could well be emitted by other language front-ends, so it's as well to have a sensible implementation. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206568 91177308-0d34-0410-b5e6-96231b3b80d8
* This commit allows vectorized loops to be unrolled by a factor of 2 for AArch64.Jiangning Liu2014-04-18
| | | | | | | | | | A new test case is also added for ARM64. Patched by Z.Zheng git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206563 91177308-0d34-0410-b5e6-96231b3b80d8
* R600: Minor cleanups.Matt Arsenault2014-04-18
| | | | | | Fix indentation, better line wrapping, unused includes. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206562 91177308-0d34-0410-b5e6-96231b3b80d8
* This is one of the optimizations ported from ARM64 to AArch64 to address the ↵Jiangning Liu2014-04-18
| | | | | | | | | | performance gap between these two back ends. The test case newly added for AArch64 already exists in ARM64. Patched by Z.Zheng git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206559 91177308-0d34-0410-b5e6-96231b3b80d8
* R600/SI: Try to use scalar BFE.Matt Arsenault2014-04-18
| | | | | | | | Use scalar BFE with constant shift and offset when possible. This is complicated by the fact that the scalar version packs the two operands of the vector version into one. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206558 91177308-0d34-0410-b5e6-96231b3b80d8
* This commit enables unaligned memory accesses of vector types on AArch64 ↵Jiangning Liu2014-04-18
| | | | | | | | | | back end. This should boost vectorized code performance. Patched by Z. Zheng git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206557 91177308-0d34-0410-b5e6-96231b3b80d8
* R600/SI: Match sign_extend_inreg to s_sext_i32_i8 and s_sext_i32_i16Matt Arsenault2014-04-18
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206547 91177308-0d34-0410-b5e6-96231b3b80d8
* R600/SI: Use SReg_64 instead of VSrc_64 when selecting BUILD_PAIRTom Stellard2014-04-18
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206541 91177308-0d34-0410-b5e6-96231b3b80d8
* [ARM64,C++11] Range'ify another loop.Jim Grosbach2014-04-17
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206539 91177308-0d34-0410-b5e6-96231b3b80d8
* Start pushing changes for Mips Fast-IselReed Kotler2014-04-17
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206505 91177308-0d34-0410-b5e6-96231b3b80d8
* R600: Add comment clariying use of sext for result of MUL_U24Tom Stellard2014-04-17
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206501 91177308-0d34-0410-b5e6-96231b3b80d8
* R600/SI: Stop using i128 as the resource descriptor typeTom Stellard2014-04-17
| | | | | | | | | Having i128 as a legal type complicates the legalization phase. v4i32 is already a legal type, so we will use that instead. This fixes several piglit tests. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206500 91177308-0d34-0410-b5e6-96231b3b80d8
* R600/SI: Change default register class for i32 to SReg_32Tom Stellard2014-04-17
| | | | | | SIFixSGPRCopies is smart enough to handle this now. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206499 91177308-0d34-0410-b5e6-96231b3b80d8
* R600/SI: Teach SIInstrInfo::moveToVALU() how to handle PHI instructionsTom Stellard2014-04-17
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206498 91177308-0d34-0410-b5e6-96231b3b80d8
* R600/SI: Legalize operands after changing dst reg in FixSGPRCopiesTom Stellard2014-04-17
| | | | | | Otherwise we may not legalize some illegal REG_SEQUENCE instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206497 91177308-0d34-0410-b5e6-96231b3b80d8
* Improve ARM64 vector creationLouis Gerbarg2014-04-17
| | | | | | | | | | | This patch improves the performance of vector creation in caseiswhere where several of the lanes in the vector are a constant floating point value. It also includes new patterns to fold together some of the instructions when the value is 0.0f. Test cases included. rdar://16349427 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206496 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM64: [su]xtw use W regs as inputs, not X regs.Jim Grosbach2014-04-17
| | | | | | | | | Update the SXT[BHW]/UXTW instruction aliases and the shifted reg addressing mode handling. PR19455 and rdar://16650642 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206495 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM64: switch to IR-based atomic operations.Tim Northover2014-04-17
| | | | | | | | Goodbye code! (Game: spot the bug fixed by the change). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206490 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM64: add acquire/release versions of the existing atomic intrinsics.Tim Northover2014-04-17
| | | | | | | These will be needed to support IR-level lowering of atomic operations. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206489 91177308-0d34-0410-b5e6-96231b3b80d8
* Atomics: promote ARM's IR-based atomics pass to CodeGen.Tim Northover2014-04-17
| | | | | | | | | | | | Still only 32-bit ARM using it at this stage, but the promotion allows direct testing via opt and is a reasonably self-contained patch on the way to switching ARM64. At this point, other targets should be able to make use of it without too much difficulty if they want. (See ARM64 commit coming soon for an example). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206485 91177308-0d34-0410-b5e6-96231b3b80d8
* R600/SI: f64 frint is legal on CIMatt Arsenault2014-04-17
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206475 91177308-0d34-0410-b5e6-96231b3b80d8
* [AArch64] Implement the getCSRFirstUseCost API, mirroring that in ARM64.Chad Rosier2014-04-17
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206473 91177308-0d34-0410-b5e6-96231b3b80d8
* [X86] Add disassembler support for the 0x0f 0x7f form of movq %mm, %mm.Craig Topper2014-04-17
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206447 91177308-0d34-0410-b5e6-96231b3b80d8
* R600/SI: Fix zext from i1 to i64Matt Arsenault2014-04-17
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206437 91177308-0d34-0410-b5e6-96231b3b80d8
* [ARM64] Fix "Cannot select" for vector ctpopAdam Nemet2014-04-17
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The commit of r205855: Author: Arnold Schwaighofer <aschwaighofer@apple.com> Date: Wed Apr 9 14:20:47 2014 +0000 SLPVectorizer: Only vectorize intrinsics whose operands are widened equally The vectorizer only knows how to vectorize intrinics by widening all operands by the same factor. Patch by Tyler Nowicki! exposed a backend bug causing a regression (Cannot select ctpop). The commit msg is a bit confusing because the patch actually changes the behavior for the loop-vectorizer as well. As things got refactored into a helper ctpop got snuck in to the trivially-vectorizable helper which is now used by both vectorizers. In other words, we started seeing vector-ctpops in the backend. This change makes ctpop LegalizeAction::Expand for the types not supported by the byte-only CNT instruction. We may be able to custom-lower these later to a single CNT but this is to fix the compiler crash first. Fixes <rdar://problem/16578951> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206433 91177308-0d34-0410-b5e6-96231b3b80d8
* Replacing a non-ASCII character in a comment with an ASCII character. Fixes ↵Aaron Ballman2014-04-16
| | | | | | a C4819 warning in MSVC. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206403 91177308-0d34-0410-b5e6-96231b3b80d8
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