| Commit message (Expand) | Author | Age |
|---|
| * | [mips] brcond + setgt/setugt instruction selection patterns. | Akira Hatanaka | 2013-06-05 |
| * | Use IRBuilder instead of ConstantInt methods. It simplifies code a little bit. | Jakub Staszak | 2013-06-05 |
| * | [PATCH] Fix VGATHER* operand constraints | Michael Liao | 2013-06-05 |
| * | ARM sched model: Add more ALU and CMP instructions | Arnold Schwaighofer | 2013-06-05 |
| * | ARM sched model: Add divsion, loads, branches, vfp cvt | Arnold Schwaighofer | 2013-06-05 |
| * | ARMInstrInfo: Improve isSwiftFastImmShift | Arnold Schwaighofer | 2013-06-05 |
| * | This is a simple patch that changes RRX and RRXS to accept all registers as o... | Mihai Popa | 2013-06-05 |
| * | PR15662: Optimized debug info produces out of order function parameters | David Blaikie | 2013-06-05 |
| * | R600: Make sure to schedule AR register uses and defs in the same clause | Tom Stellard | 2013-06-05 |
| * | Don't print default values for NumberOfAuxSymbols and AuxiliaryData. | Rafael Espindola | 2013-06-05 |
| * | Handle (at least don't crash on) relocations with no symbols. | Rafael Espindola | 2013-06-05 |
| * | Move BinaryRef to a new include/llvm/Object/YAML.h file. | Rafael Espindola | 2013-06-05 |
| * | Revert "R600: Add a pass that merge Vector Register" | Rafael Espindola | 2013-06-05 |
| * | Handle relocations that don't point to symbols. | Rafael Espindola | 2013-06-05 |
| * | R600: Add a pass that merge Vector Register | Vincent Lejeune | 2013-06-04 |
| * | R600: Const/Neg/Abs can be folded to dot4 | Vincent Lejeune | 2013-06-04 |
| * | Cortex-R5 can issue Thumb2 integer division instructions. | Evan Cheng | 2013-06-04 |
| * | Revert series of sched model patches until I figure out what is going on. | Arnold Schwaighofer | 2013-06-04 |
| * | ARM sched model: Add VFP div instruction on Swift | Arnold Schwaighofer | 2013-06-04 |
| * | ARM sched model: Add SIMD/VFP load/store instructions on Swift | Arnold Schwaighofer | 2013-06-04 |
| * | ARM sched model: Add integer VFP/SIMD instructions on Swift | Arnold Schwaighofer | 2013-06-04 |
| * | ARM sched model: Add integer load/store instructions on Swift | Arnold Schwaighofer | 2013-06-04 |
| * | ARM sched model: Add integer arithmetic instructions on Swift | Arnold Schwaighofer | 2013-06-04 |
| * | ARM sched model: Cortex A9 - More InstRW sched resources | Arnold Schwaighofer | 2013-06-04 |
| * | ARM sched model: Add branch thumb instructions | Arnold Schwaighofer | 2013-06-04 |
| * | ARM sched model: Add branch thumb2 instructions | Arnold Schwaighofer | 2013-06-04 |
| * | ARM sched model: Add branch instructions | Arnold Schwaighofer | 2013-06-04 |
| * | ARM sched model: Add preload thumb2 instructions | Arnold Schwaighofer | 2013-06-04 |
| * | ARM sched model: Add preload instructions | Arnold Schwaighofer | 2013-06-04 |
| * | ARM sched model: Add more ALU and CMP thumb instructions | Arnold Schwaighofer | 2013-06-04 |
| * | ARM sched model: Add more ALU and CMP thumb2 instructions | Arnold Schwaighofer | 2013-06-04 |
| * | ARM sched model: Add more ALU and CMP instructions | Arnold Schwaighofer | 2013-06-04 |
| * | ARM sched model: Add divsion, loads, branches, vfp cvt | Arnold Schwaighofer | 2013-06-04 |
| * | ARMInstrInfo: Improve isSwiftFastImmShift | Arnold Schwaighofer | 2013-06-04 |
| * | Sparc: No functionality change. Cleanup whitespaces, comment formatting etc., | Venkatraman Govindaraju | 2013-06-04 |
| * | IndVarSimplify: check if loop invariant expansion can trap | David Majnemer | 2013-06-04 |
| * | ARM: Fix crash in ARM backend inside of ARMConstantIslandPass | David Majnemer | 2013-06-04 |
| * | R600: Swizzle texture/export instructions | Vincent Lejeune | 2013-06-04 |
| * | Second part of pr16069 | Rafael Espindola | 2013-06-04 |
| * | Typo: s/caes/cases/ in SimplifyCFG | Hans Wennborg | 2013-06-04 |
| * | Preserve const correctness. | Benjamin Kramer | 2013-06-04 |
| * | Test commit for user vmedic, to verify commit access. One line of comment is ... | Vladimir Medic | 2013-06-04 |
| * | Silencing an MSVC warning about mixing bool and unsigned int. | Aaron Ballman | 2013-06-04 |
| * | Silencing an MSVC warning about */ being found outside of a comment. | Aaron Ballman | 2013-06-04 |
| * | Fix a defect in code-layout pass, improving Benchmarks/Olden/em3d/em3d by abo... | Shuxin Yang | 2013-06-04 |
| * | Delete dead safety check. | Nick Lewycky | 2013-06-03 |
| * | SimplifyCFG: Do not transform PHI to select if doing so would be unsafe | David Majnemer | 2013-06-03 |
| * | SimplifyCFG: Small cleanup, use ICmpInst::isEquality() | David Majnemer | 2013-06-03 |
| * | Update RuntimeDyldELF::findOPDEntrySection the new relocation iterators. | Rafael Espindola | 2013-06-03 |
| * | R600/SI: Add support for work item and work group intrinsics | Tom Stellard | 2013-06-03 |
