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* ARMAsmParser: Plug a leak.Benjamin Kramer2013-08-03
| | | | | | Using an object to do the cleanup may look like overkill, but it's safer and nicer than putting deletes everywhere. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187696 91177308-0d34-0410-b5e6-96231b3b80d8
* Stop leaking register infos in the disassemblers.Benjamin Kramer2013-08-03
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187695 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix PPC64 64-bit GPR inline asm constraint matchingHal Finkel2013-08-03
| | | | | | | | | | | | | | | Internally, the PowerPC backend names the 32-bit GPRs R[0-9]+, and names the 64-bit parent GPRs X[0-9]+. When matching inline assembly constraints with explicit register names, on PPC64 when an i64 MVT has been requested, we need to follow gcc's convention of using r[0-9]+ to refer to the 64-bit (parent) registers. At some point, we'll probably want to arrange things so that the generic code in TargetLowering uses the AsmName fields declared in *RegisterInfo.td in order to match these inline asm register constraints. If we do that, this change can be reverted. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187693 91177308-0d34-0410-b5e6-96231b3b80d8
* Minor address space code simplification.Matt Arsenault2013-08-03
| | | | | | Remove assertion that the verifier should catch. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187692 91177308-0d34-0410-b5e6-96231b3b80d8
* Add a AttributeSetImpl::dump function.Peter Collingbourne2013-08-02
| | | | | | | This is for the benefit of those of us with inferior debuggers which do not permit member function calls on value types. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187685 91177308-0d34-0410-b5e6-96231b3b80d8
* Make one of the AttributeSet ctors maintain the invariant that thePeter Collingbourne2013-08-02
| | | | | | | | attribute list is ordered by index. Differential Revision: http://llvm-reviews.chandlerc.com/D1265 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187682 91177308-0d34-0410-b5e6-96231b3b80d8
* Option parsing: recognize the special -- tokenHans Wennborg2013-08-02
| | | | | | | | | | | | | | Everything that comes after -- should be treated as a filename. This enables passing in filenames that would otherwise be conflated with command-line options. This is especially important for clang-cl which supports options starting with /, which are easily conflatable with Unix-style path names. Differential Revision: http://llvm-reviews.chandlerc.com/D1274 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187675 91177308-0d34-0410-b5e6-96231b3b80d8
* Add a missing 'return' statement.Joey Gouly2013-08-02
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187671 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips] Expand vector truncating stores and extending loads.Akira Hatanaka2013-08-02
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187667 91177308-0d34-0410-b5e6-96231b3b80d8
* [ARMv8] Add an assembler warning for the deprecated 'setend' instruction.Joey Gouly2013-08-02
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187666 91177308-0d34-0410-b5e6-96231b3b80d8
* SLPVectorizer: Fix PR16777. PHInodes may use multiple extracted values that ↵Nadav Rotem2013-08-02
| | | | | | | | | | come from different blocks. Thanks Alexey Samsonov. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187663 91177308-0d34-0410-b5e6-96231b3b80d8
* Fixes ARM LNT bot from SLP change in O3Renato Golin2013-08-02
| | | | | | | | | | | | This patch fixes the multiple breakages on ARM test-suite after the SLP vectorizer was introduced by default on O3. The problem was an illegal vector type on ARMTTI::getCmpSelInstrCost() <3 x i1> which is not simple. The guard protects this code from breaking (cause of the problems) but doesn't fix the issue that is generating the odd vector in the first place, which also needs to be investigated. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187658 91177308-0d34-0410-b5e6-96231b3b80d8
* Bugfix for making the DWARF debug strings and labels to code emitted as ↵Carlo Kok2013-08-02
| | | | | | secrel32 instead of long opcodes (only for coff). This makes them debuggable with GDB (with fix for 64bits msvc) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187656 91177308-0d34-0410-b5e6-96231b3b80d8
* Pacify GCC, which worries about falling off the end of the switch.Duncan Sands2013-08-02
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187649 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix dereferencing end iterator in SimplifyCFG. Patch by Ye Mei.Alexey Samsonov2013-08-02
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187646 91177308-0d34-0410-b5e6-96231b3b80d8
* Revert r187597, "Bugfix for making the DWARF debug strings and labels to ↵NAKAMURA Takumi2013-08-02
| | | | | | | | code emitted as secrel32 instead of long opcodes (only for coff). This makes them debuggable with GDB." It broke x86_64-win32 builder in llvm/test/DebugInfo. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187642 91177308-0d34-0410-b5e6-96231b3b80d8
* Temporarily revert "Debug Info Finder|Verifier: handle DbgLoc attached toEric Christopher2013-08-02
| | | | | | | | instructions." in an attempt to bring back some bots. This reverts commit r187609. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187638 91177308-0d34-0410-b5e6-96231b3b80d8
* Teach InstructionSimplify about pointer address spacesMatt Arsenault2013-08-02
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187635 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips] Make load/store accumulator pseudo instructions codeGenOnly. Also,Akira Hatanaka2013-08-01
| | | | | | | | | remove lines that are setting DecoderNamespace for pseudo atomic instructions. No intended functionality change. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187632 91177308-0d34-0410-b5e6-96231b3b80d8
* Teach getOrEnforceKnownAlignment about address spacesMatt Arsenault2013-08-01
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187629 91177308-0d34-0410-b5e6-96231b3b80d8
* Move the optlevel check to the frontend.Nadav Rotem2013-08-01
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187628 91177308-0d34-0410-b5e6-96231b3b80d8
* Use function attributes to indicate that we don't want to realign the stack.Bill Wendling2013-08-01
| | | | | | | | | Function attributes are the future! So just query whether we want to realign the stack directly from the function instead of through a random target options structure. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187618 91177308-0d34-0410-b5e6-96231b3b80d8
* Fixed the Intel-syntax X86 disassembler to respect the (existing) option for ↵Daniel Malea2013-08-01
| | | | | | | | | | | hexadecimal immediates, to match AT&T syntax. This also brings a new option for C-vs-MASM-style hex. Patch by Richard Mitton Reviewed: http://llvm-reviews.chandlerc.com/D1243 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187614 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix some issues with Mips16 floating when certain intrinsics are present.Reed Kotler2013-08-01
| | | | | | | | | | | | | | | | | This is actually an LLVM bug in the way it generates signatures for these when soft float is enabled. For example, floor ends up having the signature of int64(int64). The signature part is not the same as where the actual parameter types are recorded, and those ARE of course int64(int64) when soft float is enabled. (Yes, Mips16 hard float uses soft float but with different runtime rounes but then has to interoperate with Mips32 using normal floating point). This logic will eventually be moved to the Mips16HardFloat pass so it's not worth sorting out these issues in LLVM since nobody but Mips16 cares about these signatures, as far as I know, and even I won't eventually either. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187613 91177308-0d34-0410-b5e6-96231b3b80d8
* Debug Info Finder|Verifier: handle DbgLoc attached to instructions.Manman Ren2013-08-01
| | | | | | | | | | | | | | | | | | | | | | | | | Also remove checking of llvm.dbg.sp since it is not used in generating dwarf. Current state of Finder: DebugInfoFinder tries to list all debug info MDNodes used in a module. To list debug info MDNodes used by an instruction, DebugInfoFinder provides processDeclare, processValue and processLocation to handle DbgDeclareInst, DbgValueInst and DbgLoc attached to instructions. processModule will go through all DICompileUnits in llvm.dbg.cu and list debug info MDNodes used by the CUs. TODO: 1> Finder has a list of CUs, SPs, Types, Scopes and global variables. We need to add a list of variables that are used by DbgDeclareInst and DbgValueInst. 2> MDString fields should be null or isa<MDString> and MDNode fields should be null or isa<MDNode>. We currently use empty string or int 0 to represent null. 3> Go though Verify functions and make sure that they check field types. 4> Clean up existing testing cases to remove llvm.dbg.sp and make sure each testing case has a llvm.dbg.cu. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187609 91177308-0d34-0410-b5e6-96231b3b80d8
* DebugInfo: Emit definitions for types with no members.David Blaikie2013-08-01
| | | | | | The absence of members was a poor/incorrect proxy for "is definition". git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187607 91177308-0d34-0410-b5e6-96231b3b80d8
* Bugfix for making the DWARF debug strings and labels to code emitted as ↵Carlo Kok2013-08-01
| | | | | | | | secrel32 instead of long opcodes (only for coff). This makes them debuggable with GDB. fixes Bug 16249 - LLVM generates broken debug info on Windows git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187597 91177308-0d34-0410-b5e6-96231b3b80d8
* Only enable SLP-vectorization on O3 builds.Nadav Rotem2013-08-01
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187595 91177308-0d34-0410-b5e6-96231b3b80d8
* R600: Add 64-bit float load/store supportTom Stellard2013-08-01
| | | | | | | | | | | | | | | | | | * Added R600_Reg64 class * Added T#Index#.XY registers definition * Added v2i32 register reads from parameter and global space * Added f32 and i32 elements extraction from v2f32 and v2i32 * Added v2i32 -> v2f32 conversions Tom Stellard: - Mark vec2 operations as expand. The addition of a vec2 register class made them all legal. Patch by: Dmitry Cherkassov Signed-off-by: Dmitry Cherkassov <dcherkassov@gmail.com> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187582 91177308-0d34-0410-b5e6-96231b3b80d8
* R600: Use 64-bit alignment for 64-bit kernel argumentsTom Stellard2013-08-01
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187581 91177308-0d34-0410-b5e6-96231b3b80d8
* R600/SI: Custom lower i64 ZERO_EXTENDTom Stellard2013-08-01
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187580 91177308-0d34-0410-b5e6-96231b3b80d8
* EVEX and compressed displacement encoding for AVX512Elena Demikhovsky2013-08-01
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187576 91177308-0d34-0410-b5e6-96231b3b80d8
* [SystemZ] Reuse CC results for integer comparisons with zeroRichard Sandiford2013-08-01
| | | | | | | | | | | This also fixes a bug in the predication of LR to LOCR: I'd forgotten that with these in-place instruction builds, the implicit operands need to be added manually. I think this was latent until now, but is tested by int-cmp-45.c. It also adds a CC valid mask to STOC, again tested by int-cmp-45.c. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187573 91177308-0d34-0410-b5e6-96231b3b80d8
* [SystemZ] Prefer comparisons with zeroRichard Sandiford2013-08-01
| | | | | | | | Convert >= 1 to > 0, etc. Using comparison with zero isn't a win on its own, but it exposes more opportunities for CC reuse (the next patch). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187571 91177308-0d34-0410-b5e6-96231b3b80d8
* Moving definition of MnemonicContainsDot field from class Instruction to ↵Vladimir Medic2013-08-01
| | | | | | class AsmParser as suggested. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187569 91177308-0d34-0410-b5e6-96231b3b80d8
* AArch64: add initial NEON supportTim Northover2013-08-01
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Patch by Ana Pazos. - Completed implementation of instruction formats: AdvSIMD three same AdvSIMD modified immediate AdvSIMD scalar pairwise - Completed implementation of instruction classes (some of the instructions in these classes belong to yet unfinished instruction formats): Vector Arithmetic Vector Immediate Vector Pairwise Arithmetic - Initial implementation of instruction formats: AdvSIMD scalar two-reg misc AdvSIMD scalar three same - Intial implementation of instruction class: Scalar Arithmetic - Initial clang changes to support arm v8 intrinsics. Note: no clang changes for scalar intrinsics function name mangling yet. - Comprehensive test cases for added instructions To verify auto codegen, encoding, decoding, diagnosis, intrinsics. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187567 91177308-0d34-0410-b5e6-96231b3b80d8
* XCore target: Fix Vararg handlingRobert Lytton2013-08-01
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187565 91177308-0d34-0410-b5e6-96231b3b80d8
* XCore target: Add byval handlingRobert Lytton2013-08-01
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187563 91177308-0d34-0410-b5e6-96231b3b80d8
* Xcore targetRobert Lytton2013-08-01
| | | | | | Fix emitArrayBound() calling OutStreamer.Emit*() multiple times when trying to print a single line git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187562 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix some misc. issues with Mips16 fp stubs.Reed Kotler2013-08-01
| | | | | | | | | | 1) They should never be inlined. 2) A naming inconsistency with gcc mips16 3) Stubs should not have the global attribute git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187555 91177308-0d34-0410-b5e6-96231b3b80d8
* Add an omitted IsCall=1.Reed Kotler2013-08-01
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187553 91177308-0d34-0410-b5e6-96231b3b80d8
* Option parsing: add support for alias arguments.Hans Wennborg2013-07-31
| | | | | | | | | | | | | | | | | | This makes option aliases more powerful by enabling them to pass along arguments to the option they're aliasing. For example, if we have a joined option "-foo=", we can now specify a flag option "-bar" to be an alias of that, with the argument "baz". This is especially useful for the cl.exe compatible clang driver, where many options are aliases. For example, this patch enables us to alias "/Ox" to "-O3" (-O is a joined option), and "/WX" to "-Werror" (again, -W is a joined option). Differential Revision: http://llvm-reviews.chandlerc.com/D1245 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187537 91177308-0d34-0410-b5e6-96231b3b80d8
* 80-colNadav Rotem2013-07-31
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187535 91177308-0d34-0410-b5e6-96231b3b80d8
* Added the B9.3.19 SUBS PC, LR, #imm (Thumb2) system instruction.Kevin Enderby2013-07-31
| | | | | | | | | | | | While the .td entry is nice and all, it takes a pretty gross hack in ARMAsmParser::ParseInstruction() because of handling of other "subs" instructions to get it to match. Ran it by Jim Grosbach and he said it was about what he expected to make this work given the existing code. rdar://14214063 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187530 91177308-0d34-0410-b5e6-96231b3b80d8
* Revert "R600: Non vector only instruction can be scheduled on trans unit"Tom Stellard2013-07-31
| | | | | | This reverts commit 98ce62780ea7185ba710868bf83c8077e8d7f6d6. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187526 91177308-0d34-0410-b5e6-96231b3b80d8
* Revert "R600: Use SchedModel enum for is{Trans,Vector}Only functions"Tom Stellard2013-07-31
| | | | | | This reverts commit 3f1de26cb5cc0543a6a1d71259a7a39d97139051. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187524 91177308-0d34-0410-b5e6-96231b3b80d8
* R600: Do not mergevector after a vector reg is usedVincent Lejeune2013-07-31
| | | | | | | | | | If we merge vector when a vector is used, it will generate an artificial antidependency that can prevent 2 tex/vtx instructions to use the same clause and thus generate extra clauses that reduce performance. There is no test case as such situation is really hard to predict. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187516 91177308-0d34-0410-b5e6-96231b3b80d8
* R600: Avoid more than 4 literals in the same instruction group at schedulingVincent Lejeune2013-07-31
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187515 91177308-0d34-0410-b5e6-96231b3b80d8
* R600: Non vector only instruction can be scheduled on trans unitVincent Lejeune2013-07-31
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187514 91177308-0d34-0410-b5e6-96231b3b80d8
* R600: Don't mix LDS and non-LDS instructions in the same groupVincent Lejeune2013-07-31
| | | | | | | | There are a lot of restrictions on instruction groups that contain LDS instructions, so for now we will be conservative and not packetize anything else with them. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187513 91177308-0d34-0410-b5e6-96231b3b80d8
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