| Commit message (Expand) | Author | Age |
|---|
| ... | |
| * | [Sparc] Delete FPMover Pass and remove Fp* Pseudo-instructions from Sparc bac... | Venkatraman Govindaraju | 2013-06-08 |
| * | ARM: fix VMOVvnf32 decoding when ambiguous with VCVT | Amaury de la Vieuville | 2013-06-08 |
| * | ARM: enforce SRS decoding constraints | Amaury de la Vieuville | 2013-06-08 |
| * | ARM: fix CPS decoding when ambiguous with QADD | Amaury de la Vieuville | 2013-06-08 |
| * | ARM: fix VCVT decoding | Amaury de la Vieuville | 2013-06-08 |
| * | Fix a potential bug in r183584. | Shuxin Yang | 2013-06-08 |
| * | Don't artifically restrict input object size. | Sean Silva | 2013-06-08 |
| * | Fix unused variable warning from my previous patch. | JF Bastien | 2013-06-08 |
| * | [mips] Use a helper function which compares the size of the source and | Akira Hatanaka | 2013-06-08 |
| * | Reapply r183552. This time, use a standard type for the option to avoid template | Quentin Colombet | 2013-06-08 |
| * | R600: Use a refined heuristic to choose when switching clause | Vincent Lejeune | 2013-06-07 |
| * | R600: Anti dep better handled in tex clause | Vincent Lejeune | 2013-06-07 |
| * | Remember the anyext patterns. | Jakob Stoklund Olesen | 2013-06-07 |
| * | Add missing zextloadi1 to i64 patterns. PR16721. | Jakob Stoklund Olesen | 2013-06-07 |
| * | Fix an assertion in MemCpyOpt pass. | Shuxin Yang | 2013-06-07 |
| * | Disallow i64 div/rem in PPC32 counter loops | Hal Finkel | 2013-06-07 |
| * | Revert commits related to stack warning. | Quentin Colombet | 2013-06-07 |
| * | Don't cache the instruction and register info from the TargetMachine, because | Bill Wendling | 2013-06-07 |
| * | Don't cache the instruction and register info from the TargetMachine, because | Bill Wendling | 2013-06-07 |
| * | Remove unused c'tor. | Bill Wendling | 2013-06-07 |
| * | R600: Fix calculation of stack offset in AMDGPUFrameLowering | Tom Stellard | 2013-06-07 |
| * | Don't cache the instruction and register info from the TargetMachine, because | Bill Wendling | 2013-06-07 |
| * | R600: Rework subtarget info and remove AMDILDevice classes | Tom Stellard | 2013-06-07 |
| * | Don't cache the instruction and register info from the TargetMachine, because | Bill Wendling | 2013-06-07 |
| * | Don't cache the instruction and register info from the TargetMachine, because | Bill Wendling | 2013-06-07 |
| * | R600: Fix the fetch limits for R600 generation GPUs | Tom Stellard | 2013-06-07 |
| * | R600: Move Subtarget feature definitions into AMDGPU.td | Tom Stellard | 2013-06-07 |
| * | R600: Remove unnecessary include | Tom Stellard | 2013-06-07 |
| * | Add a backend option to warn on a given stack size limit. | Quentin Colombet | 2013-06-07 |
| * | ARM FastISel integer sext/zext improvements | JF Bastien | 2013-06-07 |
| * | R600: Don't compare iterators of different maps. | Benjamin Kramer | 2013-06-07 |
| * | Teach AsmPrinter how to print odd constants. | Quentin Colombet | 2013-06-07 |
| * | DIBuilder: No functionality change. | Manman Ren | 2013-06-07 |
| * | Vincent says the element is at most once in the vector, so we don't need a fu... | Benjamin Kramer | 2013-06-07 |
| * | Use isxdigit. | Rafael Espindola | 2013-06-07 |
| * | Fix a typo in asm string of BP* family of instructions. With this fix | Roman Divacky | 2013-06-07 |
| * | Support OpenBSD's native frame protection conventions. | Rafael Espindola | 2013-06-07 |
| * | R600: Fix a potential iterator invalidation issue. | Benjamin Kramer | 2013-06-07 |
| * | R600: Remove an extra break in R600OptimizeVectorRegisters.cpp | Vincent Lejeune | 2013-06-07 |
| * | Fold variable that's only used in assert into the assert. | Benjamin Kramer | 2013-06-07 |
| * | Correct wrong register in this example, pointed out by Baoshan Pang. | Duncan Sands | 2013-06-07 |
| * | Don't cache the instruction and register info from the TargetMachine, because | Bill Wendling | 2013-06-07 |
| * | Don't cache the instruction and register info from the TargetMachine, because | Bill Wendling | 2013-06-07 |
| * | Don't cache the instruction and register info from the TargetMachine, because | Bill Wendling | 2013-06-07 |
| * | Don't cache the instruction and register info from the TargetMachine, because | Bill Wendling | 2013-06-07 |
| * | Don't cache the instruction and register info from the TargetMachine, because | Bill Wendling | 2013-06-07 |
| * | [objc-arc] Ensure that the cfg path count does not overflow when we multiply ... | Michael Gottesman | 2013-06-07 |
| * | Don't cache the instruction and register info from the TargetMachine, because | Bill Wendling | 2013-06-07 |
| * | Don't cache the instruction info and register info objects. | Bill Wendling | 2013-06-07 |
| * | DIBuilder: No functionality change. | Manman Ren | 2013-06-07 |
