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* AArch64/ARM64: use HS instead of CS & LO instead of CC.Tim Northover2014-04-30
| | | | | | | | | On instructions using the NZCV register, a couple of conditions have dual representations: HS/CS and LO/CC (meaning unsigned-higher-or-same/carry-set and unsigned-lower/carry-clear). The first of these is more descriptive in most circumstances, so we should print it. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207644 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM64: use hex immediates for movz/movk instructionsTim Northover2014-04-30
| | | | | | | | Since these are mostly used in "lsl #16", "lsl #32", "lsl #48" combinations to piece together an immediate in 16-bit chunks, hex is probably the most appropriate format. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207635 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM64: print canonical syntax for add/sub (imm) instructions.Tim Northover2014-04-30
| | | | | | | | | | Since these instructions only accept a 12-bit immediate, possibly shifted left by 12, the canonical syntax used by the architecture reference manual is "#N {, lsl #12 }". We should accept an immediate that has already been shifted, (e.g. Also, print a comment giving the full addend since it can be helpful. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207633 91177308-0d34-0410-b5e6-96231b3b80d8
* [ARM64] Ensure arm64_be is dealt with when emitting debug info.James Molloy2014-04-30
| | | | | | | This is a partial port of r204816 (cpirker "Elf support for MC-JIT runtime dynamic linker") from AArch64 to ARM64. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207625 91177308-0d34-0410-b5e6-96231b3b80d8
* AArch64: Mark vector long multiplication as expand.Benjamin Kramer2014-04-29
| | | | | | | There are no patterns for this. This was already fixed for ARM64 but I forgot to apply it to AArch64 too. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207515 91177308-0d34-0410-b5e6-96231b3b80d8
* [ARM64] Print preferred aliases for SFBM/UBFM in InstPrinterBradley Smith2014-04-25
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207219 91177308-0d34-0410-b5e6-96231b3b80d8
* [ARM64] Add RUN lines for "–target arm64 –mattr=-fp-armv8" on AArch64 ↵Kevin Qin2014-04-25
| | | | | | | | | | no-fp test. This patch is a supplement of implementing predicate of FP, enabling aarch64 backend no-fp tests on arm64 target for verification. During this, one bug is exposed and fixed by this patch. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207215 91177308-0d34-0410-b5e6-96231b3b80d8
* AArch64: print NEON lists with a space.Tim Northover2014-04-24
| | | | | | | This matches ARM64 behaviour, which I think is clearer. It also puts all the churn from that difference into one easily ignored commit. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207116 91177308-0d34-0410-b5e6-96231b3b80d8
* AArch64/ARM64: port bitfield test to ARM64.Tim Northover2014-04-24
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207103 91177308-0d34-0410-b5e6-96231b3b80d8
* AArch64/ARM64: implement BFI optimisationTim Northover2014-04-24
| | | | | | | | | | | ARM64 was not producing pure BFI instructions for bitfield insertion operations, unlike AArch64. The approach had to be a little different (in ISelDAGToDAG rather than ISelLowering), and the outcomes aren't identical but hopefully this gives it similar power. This should address PR19424. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207102 91177308-0d34-0410-b5e6-96231b3b80d8
* AArch64/ARM64: port more testsTim Northover2014-04-24
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207101 91177308-0d34-0410-b5e6-96231b3b80d8
* AArch64/ARM64: more testing from AArch64 to ARM64Tim Northover2014-04-22
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206889 91177308-0d34-0410-b5e6-96231b3b80d8
* AArch64/ARM64: make use of ANDS and BICS instructions for comparisons.Tim Northover2014-04-22
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206888 91177308-0d34-0410-b5e6-96231b3b80d8
* AArch64/ARM64: add extra testing from AArch64 to ARM64Tim Northover2014-04-22
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206887 91177308-0d34-0410-b5e6-96231b3b80d8
* AArch64/ARM64: enable various AArch64 tests on ARM64.Tim Northover2014-04-22
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206877 91177308-0d34-0410-b5e6-96231b3b80d8
* AArch64/ARM64: add patterns for scalar_to_vector/extract pairsTim Northover2014-04-22
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206876 91177308-0d34-0410-b5e6-96231b3b80d8
* AArch64/ARM64: mark fmul intrinsic as commutative.Tim Northover2014-04-22
| | | | | | | This gives DAG patterns matching indexed patterns where either side is an indexed vector. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206875 91177308-0d34-0410-b5e6-96231b3b80d8
* [AArch64] Enable global merge pass.Jiangning Liu2014-04-22
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206861 91177308-0d34-0410-b5e6-96231b3b80d8
* AArch64/ARM64: add more NEON tests.Tim Northover2014-04-18
| | | | | | | Mostly no testing this time, since they were just wrangling target-specific intrinsics. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206613 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM64: add extra NEG pattern.Tim Northover2014-04-18
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206609 91177308-0d34-0410-b5e6-96231b3b80d8
* AArch64/ARM64: port more AArch64 tests to ARM64.Tim Northover2014-04-18
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206592 91177308-0d34-0410-b5e6-96231b3b80d8
* AArch64/ARM64: improve spotting of EXT instructions from VECTOR_SHUFFLE.Tim Northover2014-04-18
| | | | | | | We couldn't cope if the first mask element was UNDEF before, which isn't ideal. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206588 91177308-0d34-0410-b5e6-96231b3b80d8
* AArch64/ARM64: port atomics test to ARM64.Tim Northover2014-04-18
| | | | | | | Covers quite a few extra instructions (like any of the max/min ones which were broken until recently on ARM64). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206575 91177308-0d34-0410-b5e6-96231b3b80d8
* AArch64/ARM64: spot a greater variety of concat_vector operations.Tim Northover2014-04-18
| | | | | | | | | | Code mostly copied from AArch64, just tidied up a trifle and plumbed into the ARM64 way of doing things. This also enables the AArch64 tests which inspired the previous untested commits. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206574 91177308-0d34-0410-b5e6-96231b3b80d8
* AArch64/ARM64: emit all vector FP comparisons as such.Tim Northover2014-04-18
| | | | | | | | | | | | ARM64 was scalarizing some vector comparisons which don't quite map to AArch64's compare and mask instructions. AArch64's approach of sacrificing a little efficiency to emulate them with the limited set available was better, so I ported it across. More "inspired by" than copy/paste since the backend's internal expectations were a bit different, but the tests were invaluable. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206570 91177308-0d34-0410-b5e6-96231b3b80d8
* AArch64/ARM64: port BSL logic from AArch64 & enable test.Tim Northover2014-04-18
| | | | | | | | | | | I enhanced it a little in the process. The decision shouldn't really be beased on whether a BUILD_VECTOR is a splat: any set of constants will do the job provided they're related in the correct way. Also, the BUILD_VECTOR could be any operand of the incoming AND nodes, so it's best to check for all 4 possibilities rather than assuming it'll be the RHS. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206569 91177308-0d34-0410-b5e6-96231b3b80d8
* AArch64/ARM64: copy byval implementation from AArch64.Tim Northover2014-04-18
| | | | | | | | It's not actually used to handle C or C++ ABI rules on ARM64, but could well be emitted by other language front-ends, so it's as well to have a sensible implementation. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206568 91177308-0d34-0410-b5e6-96231b3b80d8
* This is one of the optimizations ported from ARM64 to AArch64 to address the ↵Jiangning Liu2014-04-18
| | | | | | | | | | performance gap between these two back ends. The test case newly added for AArch64 already exists in ARM64. Patched by Z.Zheng git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206559 91177308-0d34-0410-b5e6-96231b3b80d8
* This commit enables unaligned memory accesses of vector types on AArch64 ↵Jiangning Liu2014-04-18
| | | | | | | | | | back end. This should boost vectorized code performance. Patched by Z. Zheng git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206557 91177308-0d34-0410-b5e6-96231b3b80d8
* AArch64/ARM64: port some NEON tests to ARM64Tim Northover2014-04-16
| | | | | | | | | These ones used completely different sets of intrinsics, so the only way to do it is create a separate ARM64 copy and change them all. Other than that, CodeGen was straightforward, no deficiencies detected here. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206392 91177308-0d34-0410-b5e6-96231b3b80d8
* AArch64/ARM64: add another set of tests from AArch64Tim Northover2014-04-16
| | | | | | Another batch with no code changes. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206381 91177308-0d34-0410-b5e6-96231b3b80d8
* AArch64/ARM64: port across stub handling for ELF C++ exceptions.Tim Northover2014-04-16
| | | | | | | | The most important part here is that we should actuall emit the stubs we refer to in the exception table, but as a side issue this uses more sensible & GCC compatible representations for some of the bits of information. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206380 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM64: use 32-bit moves for constants where possible.Tim Northover2014-04-16
| | | | | | | | | | | | If we know that a particular 64-bit constant has all high bits zero, then we can rely on the fact that 32-bit ARM64 instructions automatically zero out the high bits of an x-register. This gives the expansion logic less constraints to satisfy and so sometimes allows it to pick better sequences. Came up while porting test/CodeGen/AArch64/movw-consts.ll: this will allow a 32-bit MOVN to be used in @test8 soon. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206379 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM64: use the integrated assembler on ELF.Tim Northover2014-04-16
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206378 91177308-0d34-0410-b5e6-96231b3b80d8
* DAGCombiner: don't optimise non-existant litpool loadTim Northover2014-04-16
| | | | | | | | | | | This particular DAG combine is designed to kick in when both ConstantFPs will end up being loaded via a litpool, however those nodes have a semi-legal status, dictated by isFPImmLegal so in some cases there wouldn't have been a litpool in the first place. Don't try to be clever in those circumstances. Picked up while merging some AArch64 tests. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206365 91177308-0d34-0410-b5e6-96231b3b80d8
* [ARM64] Set default CPU to generic instead of cyclone.Quentin Colombet2014-04-15
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206313 91177308-0d34-0410-b5e6-96231b3b80d8
* AArch64/ARM64: enable more AArch64 tests on ARM64.Tim Northover2014-04-15
| | | | | | No code changes for this bunch, just some test rejigs. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206291 91177308-0d34-0410-b5e6-96231b3b80d8
* AArch64/ARM64: add missing pattern for extending load.Tim Northover2014-04-15
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206290 91177308-0d34-0410-b5e6-96231b3b80d8
* AArch64/ARM64: only mangle MOVZ/MOVN during encoding when neededTim Northover2014-04-15
| | | | | | | | Sometimes we need emit the bits that would actually be a MOVN when producing a relocated MOVZ instruction (don't ask). But not always, a check which ARM64 got wrong until now. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206289 91177308-0d34-0410-b5e6-96231b3b80d8
* AArch64/ARM64: add support for large code-model jump tables.Tim Northover2014-04-15
| | | | | | | I've left the MachO CodeGen as it is, there's a reasonable chance it should use the GOT like ConstPools, but I'm not certain. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206288 91177308-0d34-0410-b5e6-96231b3b80d8
* AArch64/ARM64: add patterns for various commutations of FNMADD.Tim Northover2014-04-15
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206287 91177308-0d34-0410-b5e6-96231b3b80d8
* AArch64/ARM64: add half as a storage type on ARM64.Tim Northover2014-04-15
| | | | | | | This brings it into line with the AArch64 behaviour and should open the way for certain OpenCL features. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206286 91177308-0d34-0410-b5e6-96231b3b80d8
* AArch64/ARM64: copy patterns for fixed-point conversionsTim Northover2014-04-15
| | | | | | | | Code is mostly copied directly across, with a slight extension of the ISelDAGToDAG function so that it can cope with the floating-point constants being behind a litpool. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206285 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM64: add constraints to various FastISel operationsTim Northover2014-04-15
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206284 91177308-0d34-0410-b5e6-96231b3b80d8
* AArch64/ARM64: add more arm64 lines to AArch64 regression testsTim Northover2014-04-15
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206282 91177308-0d34-0410-b5e6-96231b3b80d8
* AArch64/ARM64: add dp tests from AArch64Tim Northover2014-04-15
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206281 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM64: specify full triple in tests to pacify Windows.Tim Northover2014-04-14
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206175 91177308-0d34-0410-b5e6-96231b3b80d8
* AArch64: add newline to end of test files.Tim Northover2014-04-14
| | | | | | Should be no other change. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206174 91177308-0d34-0410-b5e6-96231b3b80d8
* AArch64/ARM64: enable directcond.ll test on ARM64.Tim Northover2014-04-14
| | | | | | | Code change is because optimizeCompareInstr didn't know how to pull the condition code out of FCSEL instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206171 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM64: add patterns for csXYZ with reversed operands.Tim Northover2014-04-14
| | | | | | | AArch64 tests for this, and it's obviously a good idea. Have to invert the condition code, of course. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206170 91177308-0d34-0410-b5e6-96231b3b80d8
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